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Commit 4390e622 authored by Nicolin Chen's avatar Nicolin Chen Committed by Shawn Guo
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ARM: imx6: Derive spdif clock from pll3_pfd3_454m 



SPDIF can derive a TX clock for playback from one of its clock sources --
spdif root clock to match its supporting sample rates. So this patch set
the spdif root clock's parent to pll3_pfd3_454m since the pll3_pfd3_454m
can approximately meet its sample rate requirement.

Signed-off-by: default avatarNicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent df79bc9c

arch/arm/mach-imx/clk-imx6q.c

+3 −0
Original line number Diff line number Diff line
@@ -475,6 +475,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) 
	if (ret)

		pr_warn("failed to set up CLKO: %d\n", ret);



	/* Audio-related clocks configuration */

	clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]);



	/* All existing boards with PCIe use LVDS1 */

	if (IS_ENABLED(CONFIG_PCI_IMX6))

		clk_set_parent(clk[lvds1_sel], clk[sata_ref]);

arch/arm/mach-imx/clk-imx6sl.c

+3 −0
Original line number Diff line number Diff line
@@ -261,6 +261,9 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) 
		clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);

	}



	/* Audio-related clocks configuration */

	clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);



	np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");

	base = of_iomap(np, 0);

	WARN_ON(!base);