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Commit 434440a2 authored by Venkatesh Pallipadi's avatar Venkatesh Pallipadi Committed by Linus Torvalds
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[PATCH] x86: bug fix in P6 Machine check initialization 



Make P6 MCA initialization code complaint with guidelines in IA-32 SDM
Vol3.  Bank 0 control register should not be set by OS and clear status
registers on all banks on reset.

This will prevent false MCE alarms on the systems that has some non-MCE
information left-over in MC0_STATUS on reboot.

Signed-off-by: default avatarVenkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 251e6912

arch/i386/kernel/cpu/mcheck/p6.c

+8 −3
Original line number Diff line number Diff line
@@ -102,11 +102,16 @@ void __devinit intel_p6_mcheck_init(struct cpuinfo_x86 *c) 
		wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);

	nr_mce_banks = l & 0xff;



	/* Don't enable bank 0 on intel P6 cores, it goes bang quickly. */

	for (i=1; i<nr_mce_banks; i++) {

	/*

	 * Following the example in IA-32 SDM Vol 3:

	 * - MC0_CTL should not be written

	 * - Status registers on all banks should be cleared on reset

	 */

	for (i=1; i<nr_mce_banks; i++)

		wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);



	for (i=0; i<nr_mce_banks; i++)

		wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);

	}



	set_in_cr4 (X86_CR4_MCE);

	printk (KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",