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Commit 41f1219f authored by Laurent Pinchart's avatar Laurent Pinchart
Browse files

sh-pfc: Move GPIO registers access functions to gpio.c 



Move the sh_pfc_setup_data_regs(), sh_pfc_setup_data_reg(),
sh_pfc_get_data_reg(), sh_pfc_read_bit() and sh_pfc_write_bit()
function to gpio.c as they belong to the GPIO implementation. Inline
sh_pfc_read_bit() and sh_pfc_write_bit() in their only call location.

Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent fd9d05b0

drivers/pinctrl/sh-pfc/core.c

+5 −105
Original line number Diff line number Diff line
@@ -55,8 +55,7 @@ static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev) 
	return 0;

}



static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,

					 unsigned long address)

void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, unsigned long address)

{

	struct sh_pfc_window *window;

	int k;
@@ -111,7 +110,7 @@ static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r) 
	return 1;

}



static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,

unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,

				  unsigned long reg_width)

{

	switch (reg_width) {
@@ -127,8 +126,8 @@ static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg, 
	return 0;

}



static void sh_pfc_write_raw_reg(void __iomem *mapped_reg,

				 unsigned long reg_width, unsigned long data)

void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,

			  unsigned long data)

{

	switch (reg_width) {

	case 8:
@@ -145,37 +144,6 @@ static void sh_pfc_write_raw_reg(void __iomem *mapped_reg, 
	BUG();

}



int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos)

{

	unsigned long pos;



	pos = dr->reg_width - (in_pos + 1);



	pr_debug("read_bit: addr = %lx, pos = %ld, "

		 "r_width = %ld\n", dr->reg, pos, dr->reg_width);



	return (sh_pfc_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;

}



void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,

		      unsigned long value)

{

	unsigned long pos;



	pos = dr->reg_width - (in_pos + 1);



	pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "

		 "r_width = %ld\n",

		 dr->reg, !!value, pos, dr->reg_width);



	if (value)

		set_bit(pos, &dr->reg_shadow);

	else

		clear_bit(pos, &dr->reg_shadow);



	sh_pfc_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);

}



static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,

				     struct pinmux_cfg_reg *crp,

				     unsigned long in_pos,
@@ -242,73 +210,6 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc, 
	sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);

}



static void sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio)

{

	struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio];

	struct pinmux_data_reg *data_reg;

	int k, n;



	k = 0;

	while (1) {

		data_reg = pfc->info->data_regs + k;



		if (!data_reg->reg_width)

			break;



		data_reg->mapped_reg = sh_pfc_phys_to_virt(pfc, data_reg->reg);



		for (n = 0; n < data_reg->reg_width; n++) {

			if (data_reg->enum_ids[n] == gpiop->enum_id) {

				gpiop->flags &= ~PINMUX_FLAG_DREG;

				gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);

				gpiop->flags &= ~PINMUX_FLAG_DBIT;

				gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);

				return;

			}

		}

		k++;

	}



	BUG();

}



static void sh_pfc_setup_data_regs(struct sh_pfc *pfc)

{

	struct pinmux_data_reg *drp;

	int k;



	for (k = 0; k < pfc->info->nr_pins; k++) {

		if (pfc->info->pins[k].enum_id == 0)

			continue;



		sh_pfc_setup_data_reg(pfc, k);

	}



	k = 0;

	while (1) {

		drp = pfc->info->data_regs + k;



		if (!drp->reg_width)

			break;



		drp->reg_shadow = sh_pfc_read_raw_reg(drp->mapped_reg,

						      drp->reg_width);

		k++;

	}

}



void sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,

			 struct pinmux_data_reg **drp, int *bitp)

{

	struct sh_pfc_pin *gpiop = sh_pfc_get_pin(pfc, gpio);

	int k, n;



	k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;

	n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;

	*drp = pfc->info->data_regs + k;

	*bitp = n;

}



static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,

				 struct pinmux_cfg_reg **crp, int *fieldp,

				 int *valuep, unsigned long **cntp)
@@ -518,7 +419,6 @@ static int sh_pfc_probe(struct platform_device *pdev) 
	spin_lock_init(&pfc->lock);



	pinctrl_provide_dummies();

	sh_pfc_setup_data_regs(pfc);



	/*

	 * Initialize pinctrl bindings first

drivers/pinctrl/sh-pfc/core.h

+6 −5
Original line number Diff line number Diff line
@@ -46,11 +46,12 @@ int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc); 
int sh_pfc_register_pinctrl(struct sh_pfc *pfc);

int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc);



int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos);

void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,

		      unsigned long value);

void sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,

			 struct pinmux_data_reg **drp, int *bitp);

void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, unsigned long address);

unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,

				  unsigned long reg_width);

void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,

			  unsigned long data);



struct sh_pfc_pin *sh_pfc_get_pin(struct sh_pfc *pfc, unsigned int pin);

int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type,

		      int cfg_mode);

drivers/pinctrl/sh-pfc/gpio.c

+86 −6
Original line number Diff line number Diff line
@@ -36,6 +36,71 @@ static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc) 
	return gpio_to_pfc_chip(gc)->pfc;

}



static void gpio_get_data_reg(struct sh_pfc *pfc, unsigned int gpio,

			      struct pinmux_data_reg **dr, unsigned int *bit)

{

	struct sh_pfc_pin *gpiop = sh_pfc_get_pin(pfc, gpio);



	*dr = pfc->info->data_regs

	    + ((gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT);

	*bit = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;

}



static void gpio_setup_data_reg(struct sh_pfc *pfc, unsigned gpio)

{

	struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio];

	struct pinmux_data_reg *data_reg;

	int k, n;



	k = 0;

	while (1) {

		data_reg = pfc->info->data_regs + k;



		if (!data_reg->reg_width)

			break;



		data_reg->mapped_reg = sh_pfc_phys_to_virt(pfc, data_reg->reg);



		for (n = 0; n < data_reg->reg_width; n++) {

			if (data_reg->enum_ids[n] == gpiop->enum_id) {

				gpiop->flags &= ~PINMUX_FLAG_DREG;

				gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);

				gpiop->flags &= ~PINMUX_FLAG_DBIT;

				gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);

				return;

			}

		}

		k++;

	}



	BUG();

}



static void gpio_setup_data_regs(struct sh_pfc *pfc)

{

	struct pinmux_data_reg *drp;

	int k;



	for (k = 0; k < pfc->info->nr_pins; k++) {

		if (pfc->info->pins[k].enum_id == 0)

			continue;



		gpio_setup_data_reg(pfc, k);

	}



	k = 0;

	while (1) {

		drp = pfc->info->data_regs + k;



		if (!drp->reg_width)

			break;



		drp->reg_shadow = sh_pfc_read_raw_reg(drp->mapped_reg,

						      drp->reg_width);

		k++;

	}

}



/* -----------------------------------------------------------------------------

 * Pin GPIOs

 */
@@ -59,10 +124,19 @@ static void gpio_pin_free(struct gpio_chip *gc, unsigned offset) 
static void gpio_pin_set_value(struct sh_pfc *pfc, unsigned offset, int value)

{

	struct pinmux_data_reg *dr;

	int bit;

	unsigned long pos;

	unsigned int bit;



	sh_pfc_get_data_reg(pfc, offset, &dr, &bit);

	sh_pfc_write_bit(dr, bit, value);

	gpio_get_data_reg(pfc, offset, &dr, &bit);



	pos = dr->reg_width - (bit + 1);



	if (value)

		set_bit(pos, &dr->reg_shadow);

	else

		clear_bit(pos, &dr->reg_shadow);



	sh_pfc_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);

}



static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset)
@@ -82,10 +156,14 @@ static int gpio_pin_get(struct gpio_chip *gc, unsigned offset) 
{

	struct sh_pfc *pfc = gpio_to_pfc(gc);

	struct pinmux_data_reg *dr;

	int bit;

	unsigned long pos;

	unsigned int bit;



	sh_pfc_get_data_reg(pfc, offset, &dr, &bit);

	return sh_pfc_read_bit(dr, bit);

	gpio_get_data_reg(pfc, offset, &dr, &bit);



	pos = dr->reg_width - (bit + 1);



	return (sh_pfc_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;

}



static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
@@ -226,6 +304,8 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) 
	unsigned int i;

	int ret;



	gpio_setup_data_regs(pfc);



	/* Register the real GPIOs chip. */

	chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup);

	if (IS_ERR(chip))