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Commit 41ed7fe9 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-fixes-3.12' of git://people.freedesktop.org/~agd5f/linux into drm-fixes 

More radeon fixes for 3.12.  Kind of all over the place: UVD, DPM,
tiling, etc.

* 'drm-fixes-3.12' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon: fix hdmi audio on DCE3.0/3.1 asics
  drm/radeon/cik: fix overflow in vram fetch
  drm/radeon: add missing hdmi callbacks for rv6xx
  drm/radeon/uvd: lower msg&fb buffer requirements on UVD3
  drm/radeon: disable tests/benchmarks if accel is disabled
  drm/radeon: don't set default clocks for SI when DPM is disabled
  drm/radeon/dpm/ci: filter clocks based on voltage/clk dep tables
  drm/radeon/dpm/si: filter clocks based on voltage/clk dep tables
  drm/radeon/dpm/ni: filter clocks based on voltage/clk dep tables
  drm/radeon/dpm/btc: filter clocks based on voltage/clk dep tables
  drm/radeon/dpm: fetch the max clk from voltage dep tables helper
  drm/radeon: fix missed variable sized access
  drm/radeon: Make r100_cp_ring_info() and radeon_ring_gfx() safe (v2)
  drm/radeon/cik: Add tiling mode index for 1D tiled depth/stencil surfaces
  drm/radeon/cik: Fix encoding of number of banks in tiling configuration info
  drm/radeon/cik: Fix printing of client name on VM protection fault
  drm/radeon: additional gcc fixes for radeon_atombios.c
  drm/radeon: avoid UVD corruption on AGP cards using GPU gart
parents 36dec40c 58d327da

drivers/gpu/drm/radeon/btc_dpm.c

+51 −0
Original line number Diff line number Diff line
@@ -1168,6 +1168,23 @@ static const struct radeon_blacklist_clocks btc_blacklist_clocks[] = 
        { 25000, 30000, RADEON_SCLK_UP }

};



void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table,

						     u32 *max_clock)

{

	u32 i, clock = 0;



	if ((table == NULL) || (table->count == 0)) {

		*max_clock = clock;

		return;

	}



	for (i = 0; i < table->count; i++) {

		if (clock < table->entries[i].clk)

			clock = table->entries[i].clk;

	}

	*max_clock = clock;

}



void btc_apply_voltage_dependency_rules(struct radeon_clock_voltage_dependency_table *table,

					u32 clock, u16 max_voltage, u16 *voltage)

{
@@ -2080,6 +2097,7 @@ static void btc_apply_state_adjust_rules(struct radeon_device *rdev, 
	bool disable_mclk_switching;

	u32 mclk, sclk;

	u16 vddc, vddci;

	u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;



	if ((rdev->pm.dpm.new_active_crtc_count > 1) ||

	    btc_dpm_vblank_too_short(rdev))
@@ -2121,6 +2139,39 @@ static void btc_apply_state_adjust_rules(struct radeon_device *rdev, 
			ps->low.vddci = max_limits->vddci;

	}



	/* limit clocks to max supported clocks based on voltage dependency tables */

	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,

							&max_sclk_vddc);

	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,

							&max_mclk_vddci);

	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,

							&max_mclk_vddc);



	if (max_sclk_vddc) {

		if (ps->low.sclk > max_sclk_vddc)

			ps->low.sclk = max_sclk_vddc;

		if (ps->medium.sclk > max_sclk_vddc)

			ps->medium.sclk = max_sclk_vddc;

		if (ps->high.sclk > max_sclk_vddc)

			ps->high.sclk = max_sclk_vddc;

	}

	if (max_mclk_vddci) {

		if (ps->low.mclk > max_mclk_vddci)

			ps->low.mclk = max_mclk_vddci;

		if (ps->medium.mclk > max_mclk_vddci)

			ps->medium.mclk = max_mclk_vddci;

		if (ps->high.mclk > max_mclk_vddci)

			ps->high.mclk = max_mclk_vddci;

	}

	if (max_mclk_vddc) {

		if (ps->low.mclk > max_mclk_vddc)

			ps->low.mclk = max_mclk_vddc;

		if (ps->medium.mclk > max_mclk_vddc)

			ps->medium.mclk = max_mclk_vddc;

		if (ps->high.mclk > max_mclk_vddc)

			ps->high.mclk = max_mclk_vddc;

	}



	/* XXX validate the min clocks required for display */



	if (disable_mclk_switching) {

drivers/gpu/drm/radeon/btc_dpm.h

+2 −0
Original line number Diff line number Diff line
@@ -46,6 +46,8 @@ void btc_adjust_clock_combinations(struct radeon_device *rdev, 
				   struct rv7xx_pl *pl);

void btc_apply_voltage_dependency_rules(struct radeon_clock_voltage_dependency_table *table,

					u32 clock, u16 max_voltage, u16 *voltage);

void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table,

						     u32 *max_clock);

void btc_apply_voltage_delta_rules(struct radeon_device *rdev,

				   u16 max_vddc, u16 max_vddci,

				   u16 *vddc, u16 *vddci);

drivers/gpu/drm/radeon/ci_dpm.c

+26 −0
Original line number Diff line number Diff line
@@ -146,6 +146,8 @@ static const struct ci_pt_config_reg didt_config_ci[] = 
};



extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);

extern void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table,

							    u32 *max_clock);

extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,

				       u32 arb_freq_src, u32 arb_freq_dest);

extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
@@ -712,6 +714,7 @@ static void ci_apply_state_adjust_rules(struct radeon_device *rdev, 
	struct radeon_clock_and_voltage_limits *max_limits;

	bool disable_mclk_switching;

	u32 sclk, mclk;

	u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;

	int i;



	if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
@@ -739,6 +742,29 @@ static void ci_apply_state_adjust_rules(struct radeon_device *rdev, 
		}

	}



	/* limit clocks to max supported clocks based on voltage dependency tables */

	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,

							&max_sclk_vddc);

	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,

							&max_mclk_vddci);

	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,

							&max_mclk_vddc);



	for (i = 0; i < ps->performance_level_count; i++) {

		if (max_sclk_vddc) {

			if (ps->performance_levels[i].sclk > max_sclk_vddc)

				ps->performance_levels[i].sclk = max_sclk_vddc;

		}

		if (max_mclk_vddci) {

			if (ps->performance_levels[i].mclk > max_mclk_vddci)

				ps->performance_levels[i].mclk = max_mclk_vddci;

		}

		if (max_mclk_vddc) {

			if (ps->performance_levels[i].mclk > max_mclk_vddc)

				ps->performance_levels[i].mclk = max_mclk_vddc;

		}

	}



	/* XXX validate the min clocks required for display */



	if (disable_mclk_switching) {

drivers/gpu/drm/radeon/cik.c

+8 −9
Original line number Diff line number Diff line
@@ -2845,10 +2845,8 @@ static void cik_gpu_init(struct radeon_device *rdev) 
		rdev->config.cik.tile_config |= (3 << 0);

		break;

	}

	if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)

		rdev->config.cik.tile_config |= 1 << 4;

	else

		rdev->config.cik.tile_config |= 0 << 4;

	rdev->config.cik.tile_config |=

		((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;

	rdev->config.cik.tile_config |=

		((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;

	rdev->config.cik.tile_config |=
@@ -4456,8 +4454,8 @@ static int cik_mc_init(struct radeon_device *rdev) 
	rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);

	rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);

	/* size in MB on si */

	rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;

	rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;

	rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;

	rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;

	rdev->mc.visible_vram_size = rdev->mc.aper_size;

	si_vram_gtt_location(rdev, &rdev->mc);

	radeon_update_bandwidth_info(rdev);
@@ -4735,12 +4733,13 @@ static void cik_vm_decode_fault(struct radeon_device *rdev, 
	u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;

	u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;

	u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;

	char *block = (char *)&mc_client;

	char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,

		(mc_client >> 8) & 0xff, mc_client & 0xff, 0 };



	printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",

	printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",

	       protections, vmid, addr,

	       (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",

	       block, mc_id);

	       block, mc_client, mc_id);

}



/**

drivers/gpu/drm/radeon/ni_dpm.c

+24 −0
Original line number Diff line number Diff line
@@ -787,6 +787,7 @@ static void ni_apply_state_adjust_rules(struct radeon_device *rdev, 
	bool disable_mclk_switching;

	u32 mclk, sclk;

	u16 vddc, vddci;

	u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;

	int i;



	if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
@@ -813,6 +814,29 @@ static void ni_apply_state_adjust_rules(struct radeon_device *rdev, 
		}

	}



	/* limit clocks to max supported clocks based on voltage dependency tables */

	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,

							&max_sclk_vddc);

	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,

							&max_mclk_vddci);

	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,

							&max_mclk_vddc);



	for (i = 0; i < ps->performance_level_count; i++) {

		if (max_sclk_vddc) {

			if (ps->performance_levels[i].sclk > max_sclk_vddc)

				ps->performance_levels[i].sclk = max_sclk_vddc;

		}

		if (max_mclk_vddci) {

			if (ps->performance_levels[i].mclk > max_mclk_vddci)

				ps->performance_levels[i].mclk = max_mclk_vddci;

		}

		if (max_mclk_vddc) {

			if (ps->performance_levels[i].mclk > max_mclk_vddc)

				ps->performance_levels[i].mclk = max_mclk_vddc;

		}

	}



	/* XXX validate the min clocks required for display */



	if (disable_mclk_switching) {