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Commit 41e62b04 authored by Leonid Yegoshin's avatar Leonid Yegoshin Committed by Ralf Baechle
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MIPS: asm: r4kcache: Build flushing code for instruction cache 



Build code to invalidate an address range in the  instruction cache
using the Hit Invalidate cache operation.

Signed-off-by: default avatarLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
parent ca750649

arch/mips/include/asm/r4kcache.h

+1 −0
Original line number Diff line number Diff line
@@ -456,6 +456,7 @@ __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, ) 
__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \

	protected_, loongson2_)

__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )

__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , )

__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )

/* blast_inv_dcache_range */

__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )