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Commit 41cabbc2 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branch 'clk-fixes' into clk-next

* clk-fixes:
  clk: sunxi: pll2: Fix clock running too fast
  clk: scpi: add missing of_node_put
  clk: qoriq: fix memory leak
  imx/clk-pllv2: fix wrong do_div() usage
  imx/clk-pllv1: fix wrong do_div() usage
  clk: mmp: add linux/clk.h includes
  clk: ti: drop locking code from mux/divider drivers
  clk: ti816x: Add missing dmtimer clkdev entries
  clk: ti: fapll: fix wrong do_div() usage
  clk: ti: clkt_dpll: fix wrong do_div() usage
  clk: gpio: Get parent clk names in of_gpio_clk_setup()
parents 8da411cc 59f0ec23
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+17 −16
Original line number Diff line number Diff line
@@ -209,6 +209,8 @@ EXPORT_SYMBOL_GPL(clk_register_gpio_mux);

struct clk_gpio_delayed_register_data {
	const char *gpio_name;
	int num_parents;
	const char **parent_names;
	struct device_node *node;
	struct mutex lock;
	struct clk *clk;
@@ -222,8 +224,6 @@ static struct clk *of_clk_gpio_delayed_register_get(
{
	struct clk_gpio_delayed_register_data *data = _data;
	struct clk *clk;
	const char **parent_names;
	int i, num_parents;
	int gpio;
	enum of_gpio_flags of_flags;

@@ -248,26 +248,14 @@ static struct clk *of_clk_gpio_delayed_register_get(
		return ERR_PTR(gpio);
	}

	num_parents = of_clk_get_parent_count(data->node);

	parent_names = kcalloc(num_parents, sizeof(char *), GFP_KERNEL);
	if (!parent_names) {
		clk = ERR_PTR(-ENOMEM);
		goto out;
	}

	for (i = 0; i < num_parents; i++)
		parent_names[i] = of_clk_get_parent_name(data->node, i);

	clk = data->clk_register_get(data->node->name, parent_names,
			num_parents, gpio, of_flags & OF_GPIO_ACTIVE_LOW);
	clk = data->clk_register_get(data->node->name, data->parent_names,
			data->num_parents, gpio, of_flags & OF_GPIO_ACTIVE_LOW);
	if (IS_ERR(clk))
		goto out;

	data->clk = clk;
out:
	mutex_unlock(&data->lock);
	kfree(parent_names);

	return clk;
}
@@ -296,11 +284,24 @@ static void __init of_gpio_clk_setup(struct device_node *node,
				unsigned gpio, bool active_low))
{
	struct clk_gpio_delayed_register_data *data;
	const char **parent_names;
	int i, num_parents;

	data = kzalloc(sizeof(*data), GFP_KERNEL);
	if (!data)
		return;

	num_parents = of_clk_get_parent_count(node);

	parent_names = kcalloc(num_parents, sizeof(char *), GFP_KERNEL);
	if (!parent_names)
		return;

	for (i = 0; i < num_parents; i++)
		parent_names[i] = of_clk_get_parent_name(node, i);

	data->num_parents = num_parents;
	data->parent_names = parent_names;
	data->node = node;
	data->gpio_name = gpio_name;
	data->clk_register_get = clk_register_get;
+3 −1
Original line number Diff line number Diff line
@@ -778,8 +778,10 @@ static struct clk * __init create_one_cmux(struct clockgen *cg, int idx)
	 */
	clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
	div = get_pll_div(cg, hwc, clksel);
	if (!div)
	if (!div) {
		kfree(hwc);
		return NULL;
	}

	pct80_rate = clk_get_rate(div->clk);
	pct80_rate *= 8;
+1 −0
Original line number Diff line number Diff line
@@ -292,6 +292,7 @@ static int scpi_clocks_probe(struct platform_device *pdev)
		ret = scpi_clk_add(dev, child, match);
		if (ret) {
			scpi_clocks_remove(pdev);
			of_node_put(child);
			return ret;
		}
	}
+7 −7
Original line number Diff line number Diff line
@@ -52,7 +52,7 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
		unsigned long parent_rate)
{
	struct clk_pllv1 *pll = to_clk_pllv1(hw);
	long long ll;
	unsigned long long ull;
	int mfn_abs;
	unsigned int mfi, mfn, mfd, pd;
	u32 reg;
@@ -94,16 +94,16 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
	rate = parent_rate * 2;
	rate /= pd + 1;

	ll = (unsigned long long)rate * mfn_abs;
	ull = (unsigned long long)rate * mfn_abs;

	do_div(ll, mfd + 1);
	do_div(ull, mfd + 1);

	if (mfn_is_negative(pll, mfn))
		ll = -ll;

	ll = (rate * mfi) + ll;
		ull = (rate * mfi) - ull;
	else
		ull = (rate * mfi) + ull;

	return ll;
	return ull;
}

static struct clk_ops clk_pllv1_ops = {
+5 −4
Original line number Diff line number Diff line
@@ -79,7 +79,7 @@ static unsigned long __clk_pllv2_recalc_rate(unsigned long parent_rate,
{
	long mfi, mfn, mfd, pdf, ref_clk;
	unsigned long dbl;
	s64 temp;
	u64 temp;

	dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;

@@ -98,7 +98,8 @@ static unsigned long __clk_pllv2_recalc_rate(unsigned long parent_rate,
	temp = (u64) ref_clk * abs(mfn);
	do_div(temp, mfd + 1);
	if (mfn < 0)
		temp = -temp;
		temp = (ref_clk * mfi) - temp;
	else
		temp = (ref_clk * mfi) + temp;

	return temp;
@@ -126,7 +127,7 @@ static int __clk_pllv2_set_rate(unsigned long rate, unsigned long parent_rate,
{
	u32 reg;
	long mfi, pdf, mfn, mfd = 999999;
	s64 temp64;
	u64 temp64;
	unsigned long quad_parent_rate;

	quad_parent_rate = 4 * parent_rate;
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