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Commit 41485a90 authored by Mathias Nyman's avatar Mathias Nyman Committed by Greg Kroah-Hartman
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xhci: optimize xhci bus resume time 



We used to write the root port state changes in turn for every port,
sleeping 20ms after every port state change. Suspended usb2 ports need
two state changes, taking minimun 40ms per port.

Now instead poll the Port Link State Change (PLC) bit as
the state change to U0 will set this bit.
Suspended usb2 ports still need the extra 20ms delay, but we now change
all the port states at once so we only need to sleep 20ms once all together

Signed-off-by: default avatarMathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 9fa733f2

drivers/usb/host/xhci-hub.c

+38 −27
Original line number Diff line number Diff line
@@ -1184,6 +1184,10 @@ int xhci_bus_resume(struct usb_hcd *hcd) 
	struct xhci_bus_state *bus_state;

	u32 temp;

	unsigned long flags;

	unsigned long port_was_suspended = 0;

	bool need_usb2_u3_exit = false;

	int slot_id;

	int sret;



	max_ports = xhci_get_ports(hcd, &port_array);

	bus_state = &xhci->bus_state[hcd_index(hcd)];
@@ -1207,7 +1211,6 @@ int xhci_bus_resume(struct usb_hcd *hcd) 
		/* Check whether need resume ports. If needed

		   resume port and disable remote wakeup */

		u32 temp;

		int slot_id;



		temp = readl(port_array[port_index]);

		if (DEV_SUPERSPEED(temp))
@@ -1216,37 +1219,45 @@ int xhci_bus_resume(struct usb_hcd *hcd) 
			temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);

		if (test_bit(port_index, &bus_state->bus_suspended) &&

		    (temp & PORT_PLS_MASK)) {

			if (DEV_SUPERSPEED(temp)) {

				xhci_set_link_state(xhci, port_array,

							port_index, XDEV_U0);

			} else {

			set_bit(port_index, &port_was_suspended);

			if (!DEV_SUPERSPEED(temp)) {

				xhci_set_link_state(xhci, port_array,

						port_index, XDEV_RESUME);

				need_usb2_u3_exit = true;

			}

		} else

			writel(temp, port_array[port_index]);

	}



	if (need_usb2_u3_exit) {

		spin_unlock_irqrestore(&xhci->lock, flags);

		msleep(20);

		spin_lock_irqsave(&xhci->lock, flags);



				xhci_set_link_state(xhci, port_array,

							port_index, XDEV_U0);

	}

			/* wait for the port to enter U0 and report port link

			 * state change.

			 */

			spin_unlock_irqrestore(&xhci->lock, flags);

			msleep(20);

			spin_lock_irqsave(&xhci->lock, flags);



			/* Clear PLC */

			xhci_test_and_clear_bit(xhci, port_array, port_index,

						PORT_PLC);

	port_index = max_ports;

	while (port_index--) {

		if (!(port_was_suspended & BIT(port_index)))

			continue;

		/* Clear PLC to poll it later after XDEV_U0 */

		xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);

		xhci_set_link_state(xhci, port_array, port_index, XDEV_U0);

	}



			slot_id = xhci_find_slot_id_by_port(hcd,

					xhci, port_index + 1);

	port_index = max_ports;

	while (port_index--) {

		if (!(port_was_suspended & BIT(port_index)))

			continue;

		/* Poll and Clear PLC */

		sret = xhci_handshake(port_array[port_index], PORT_PLC,

				      PORT_PLC, 10 * 1000);

		if (sret)

			xhci_warn(xhci, "port %d resume PLC timeout\n",

				  port_index);

		xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);

		slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);

		if (slot_id)

			xhci_ring_device(xhci, slot_id);

		} else

			writel(temp, port_array[port_index]);

	}



	(void) readl(&xhci->op_regs->command);