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Commit 400dfbaa authored by Nithin Sujir's avatar Nithin Sujir Committed by David S. Miller
Browse files

tg3: Add tg3_eee_pull_config() function 



Add tg3_eee_pull_config() to pull the settings from the hardware and
populate the eee structure.

If Link Flap Avoidance is enabled, we pull the eee settings from the hw
so as not to cause a phy reset on eee config mismatch later. This
requires moving down tg3_setup_eee() below the tg3_pull_config() to not
trample existing settings.

Reviewed-by: default avatarBen Li <benli@broadcom.com>
Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarNithin Nayak Sujir <nsujir@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 9e2ecbeb

drivers/net/ethernet/broadcom/tg3.c

+47 −9
Original line number Diff line number Diff line
@@ -2320,6 +2320,46 @@ static void tg3_phy_apply_otp(struct tg3 *tp) 
	tg3_phy_toggle_auxctl_smdsp(tp, false);

}



static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)

{

	u32 val;

	struct ethtool_eee *dest = &tp->eee;



	if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))

		return;



	if (eee)

		dest = eee;



	if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))

		return;



	/* Pull eee_active */

	if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||

	    val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {

		dest->eee_active = 1;

	} else

		dest->eee_active = 0;



	/* Pull lp advertised settings */

	if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))

		return;

	dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);



	/* Pull advertised and eee_enabled settings */

	if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))

		return;

	dest->eee_enabled = !!val;

	dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);



	/* Pull tx_lpi_enabled */

	val = tr32(TG3_CPMU_EEE_MODE);

	dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);



	/* Pull lpi timer value */

	dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;

}



static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)

{

	u32 val;
@@ -2343,11 +2383,8 @@ static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up) 


		tw32(TG3_CPMU_EEE_CTRL, eeectl);



		tg3_phy_cl45_read(tp, MDIO_MMD_AN,

				  TG3_CL45_D7_EEERES_STAT, &val);



		if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||

		    val == TG3_CL45_D7_EEERES_STAT_LP_100TX)

		tg3_eee_pull_config(tp, NULL);

		if (tp->eee.eee_active)

			tp->setlpicnt = 2;

	}
@@ -9493,16 +9530,17 @@ static int tg3_reset_hw(struct tg3 *tp, bool reset_phy) 
	if (tg3_flag(tp, INIT_COMPLETE))

		tg3_abort_hw(tp, 1);



	/* Enable MAC control of LPI */

	if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)

		tg3_setup_eee(tp);



	if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&

	    !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {

		tg3_phy_pull_config(tp);

		tg3_eee_pull_config(tp, NULL);

		tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;

	}



	/* Enable MAC control of LPI */

	if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)

		tg3_setup_eee(tp);



	if (reset_phy)

		tg3_phy_reset(tp);