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Commit 3ef52f2a authored by Will Deacon's avatar Will Deacon
Browse files

ARM: mm: fix numerous hideous errors in proc-arm740.S 



The setup code in proc-arm740.S is completely broken and, as far as I
can tell, always has been. I was >this< close to ripping it out, when a
740t core-tile materialised in the office, so I've had a crack at fixing
things up:

	- Fix the ram/flash area calculations so that we actually set
	  the condition flags before testing them...
	- Fix the proc_info structure so that __cpu_io_mmu_flags are
	  defined as 0, placing the __cpu_flush pointer at the correct
	  offset
	- Re-number the registers used during __arm740_setup so that
	  we don't clobber the machine ID et al
	- Advertise Thumb support via the hwcaps, since 740T is the only
	  740 implementation.

Acked-by: default avatarHyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 82d9b0d0

arch/arm/mm/proc-arm740.S

+16 −12
Original line number Diff line number Diff line
@@ -77,24 +77,27 @@ __arm740_setup: 
	mcr	p15, 0, r0, c6,	c0		@ set area 0, default



	ldr	r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM

	ldr	r1, =(CONFIG_DRAM_SIZE >> 12)	@ size of RAM (must be >= 4KB)

	mov	r2, #10				@ 11 is the minimum (4KB)

1:	add	r2, r2, #1			@ area size *= 2

	mov	r1, r1, lsr #1

	ldr	r3, =(CONFIG_DRAM_SIZE >> 12)	@ size of RAM (must be >= 4KB)

	mov	r4, #10				@ 11 is the minimum (4KB)

1:	add	r4, r4, #1			@ area size *= 2

	movs	r3, r3, lsr #1

	bne	1b				@ count not zero r-shift

	orr	r0, r0, r2, lsl #1		@ the area register value

	orr	r0, r0, r4, lsl #1		@ the area register value

	orr	r0, r0, #1			@ set enable bit

	mcr	p15, 0, r0, c6,	c1		@ set area 1, RAM



	ldr	r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH

	ldr	r1, =(CONFIG_FLASH_SIZE >> 12)	@ size of FLASH (must be >= 4KB)

	mov	r2, #10				@ 11 is the minimum (4KB)

1:	add	r2, r2, #1			@ area size *= 2

	mov	r1, r1, lsr #1

	ldr	r3, =(CONFIG_FLASH_SIZE >> 12)	@ size of FLASH (must be >= 4KB)

	cmp	r3, #0

	moveq	r0, #0

	beq	2f

	mov	r4, #10				@ 11 is the minimum (4KB)

1:	add	r4, r4, #1			@ area size *= 2

	movs	r3, r3, lsr #1

	bne	1b				@ count not zero r-shift

	orr	r0, r0, r2, lsl #1		@ the area register value

	orr	r0, r0, r4, lsl #1		@ the area register value

	orr	r0, r0, #1			@ set enable bit

	mcr	p15, 0, r0, c6,	c2		@ set area 2, ROM/FLASH

2:	mcr	p15, 0, r0, c6,	c2		@ set area 2, ROM/FLASH



	mov	r0, #0x06

	mcr	p15, 0, r0, c2, c0		@ Region 1&2 cacheable
@@ -137,10 +140,11 @@ __arm740_proc_info: 
	.long	0x41807400

	.long	0xfffffff0

	.long	0

	.long	0

	b	__arm740_setup

	.long	cpu_arch_name

	.long	cpu_elf_name

	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT

	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_26BIT

	.long	cpu_arm740_name

	.long	arm740_processor_functions

	.long	0