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Commit 3e6dce76 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-intel-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intel 

* 'drm-intel-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intel:
  drm/i915: don't enable self-refresh on Ironlake
  drm/i915: Double check that the wait_request is not pending before warning
  Revert "drm/i915: Warn if we run out of FIFO space for a mode"
  Revert "drm/i915: Allow LVDS on pipe A on gen4+"
  Revert "drm/i915: Enable RC6 on Ironlake."
parents fbc14870 dd8849c8

drivers/gpu/drm/i915/i915_irq.c

+15 −7
Original line number Diff line number Diff line
@@ -1350,17 +1350,25 @@ void i915_hangcheck_elapsed(unsigned long data) 
		i915_seqno_passed(i915_get_gem_seqno(dev,

				&dev_priv->render_ring),

			i915_get_tail_request(dev)->seqno)) {

		bool missed_wakeup = false;



		dev_priv->hangcheck_count = 0;



		/* Issue a wake-up to catch stuck h/w. */

		if (dev_priv->render_ring.waiting_gem_seqno |

		    dev_priv->bsd_ring.waiting_gem_seqno) {

			DRM_ERROR("Hangcheck timer elapsed... GPU idle, missed IRQ.\n");

			if (dev_priv->render_ring.waiting_gem_seqno)

		if (dev_priv->render_ring.waiting_gem_seqno &&

		    waitqueue_active(&dev_priv->render_ring.irq_queue)) {

			DRM_WAKEUP(&dev_priv->render_ring.irq_queue);

			if (dev_priv->bsd_ring.waiting_gem_seqno)

			missed_wakeup = true;

		}



		if (dev_priv->bsd_ring.waiting_gem_seqno &&

		    waitqueue_active(&dev_priv->bsd_ring.irq_queue)) {

			DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);

			missed_wakeup = true;

		}



		if (missed_wakeup)

			DRM_ERROR("Hangcheck timer elapsed... GPU idle, missed IRQ.\n");

		return;

	}

drivers/gpu/drm/i915/i915_reg.h

+8 −0
Original line number Diff line number Diff line
@@ -2206,9 +2206,17 @@ 
#define  WM1_LP_SR_EN		(1<<31)

#define  WM1_LP_LATENCY_SHIFT	24

#define  WM1_LP_LATENCY_MASK	(0x7f<<24)

#define  WM1_LP_FBC_LP1_MASK	(0xf<<20)

#define  WM1_LP_FBC_LP1_SHIFT	20

#define  WM1_LP_SR_MASK		(0x1ff<<8)

#define  WM1_LP_SR_SHIFT	8

#define  WM1_LP_CURSOR_MASK	(0x3f)

#define WM2_LP_ILK		0x4510c

#define  WM2_LP_EN		(1<<31)

#define WM3_LP_ILK		0x45110

#define  WM3_LP_EN		(1<<31)

#define WM1S_LP_ILK		0x45120

#define  WM1S_LP_EN		(1<<31)



/* Memory latency timer register */

#define MLTR_ILK		0x11222

drivers/gpu/drm/i915/intel_display.c

+8 −15
Original line number Diff line number Diff line
@@ -2767,14 +2767,8 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz, 
	/* Don't promote wm_size to unsigned... */

	if (wm_size > (long)wm->max_wm)

		wm_size = wm->max_wm;

	if (wm_size <= 0) {

	if (wm_size <= 0)

		wm_size = wm->default_wm;

		DRM_ERROR("Insufficient FIFO for plane, expect flickering:"

			  " entries required = %ld, available = %lu.\n",

			  entries_required + wm->guard_size,

			  wm->fifo_size);

	}



	return wm_size;

}
@@ -3388,8 +3382,7 @@ static void ironlake_update_wm(struct drm_device *dev, int planea_clock, 
		reg_value = I915_READ(WM1_LP_ILK);

		reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |

			       WM1_LP_CURSOR_MASK);

		reg_value |= WM1_LP_SR_EN |

			     (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |

		reg_value |= (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |

			     (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;



		I915_WRITE(WM1_LP_ILK, reg_value);
@@ -5675,6 +5668,9 @@ void intel_init_clock_gating(struct drm_device *dev) 
			I915_WRITE(DISP_ARB_CTL,

					(I915_READ(DISP_ARB_CTL) |

						DISP_FBC_WM_DIS));

		I915_WRITE(WM3_LP_ILK, 0);

		I915_WRITE(WM2_LP_ILK, 0);

		I915_WRITE(WM1_LP_ILK, 0);

		}

		/*

		 * Based on the document from hardware guys the following bits
@@ -5696,7 +5692,6 @@ void intel_init_clock_gating(struct drm_device *dev) 
				   ILK_DPFC_DIS2 |

				   ILK_CLK_FBC);

		}

		if (IS_GEN6(dev))

		return;

	} else if (IS_G4X(dev)) {

		uint32_t dspclk_gate;
@@ -5758,11 +5753,9 @@ void intel_init_clock_gating(struct drm_device *dev) 
				OUT_RING(MI_FLUSH);

				ADVANCE_LP_RING();

			}

		} else {

		} else

			DRM_DEBUG_KMS("Failed to allocate render context."

				       "Disable RC6\n");

			return;

		}

	}



	if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {

drivers/gpu/drm/i915/intel_lvds.c

+0 −2
Original line number Diff line number Diff line
@@ -875,8 +875,6 @@ void intel_lvds_init(struct drm_device *dev) 


	intel_encoder->clone_mask = (1 << INTEL_LVDS_CLONE_BIT);

	intel_encoder->crtc_mask = (1 << 1);

	if (IS_I965G(dev))

		intel_encoder->crtc_mask |= (1 << 0);

	drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);

	drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);

	connector->display_info.subpixel_order = SubPixelHorizontalRGB;