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Commit 3e470eaa authored by Arun Siluvery's avatar Arun Siluvery Committed by Daniel Vetter
Browse files

drm/i915/chv: Remove pre-production workarounds 



-WaDisableDopClockGating:chv
-WaDisableSamplerPowerBypass:chv
-WaDisableGunitClockGating:chv
-WaDisableFfDopClockGating:chv
-WaDisableDopClockGating:chv

v2: Remove pre-production WA instead of restricting them
based on revision id (Ville)

For: VIZ-4090
Signed-off-by: default avatarArun Siluvery <arun.siluvery@linux.intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent b8bbac1d

drivers/gpu/drm/i915/intel_pm.c

+0 −12
Original line number Original line Diff line number Diff line
@@ -6958,18 +6958,6 @@ static void cherryview_init_clock_gating(struct drm_device *dev) 
	/* WaDisableSDEUnitClockGating:chv */

	/* WaDisableSDEUnitClockGating:chv */

	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |

	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |

		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);

		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);



	/* WaDisableGunitClockGating:chv (pre-production hw) */

	I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |

		   GINT_DIS);



	/* WaDisableFfDopClockGating:chv (pre-production hw) */

	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,

		   _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));



	/* WaDisableDopClockGating:chv (pre-production hw) */

	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |

		   GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);

}

}





static void g4x_init_clock_gating(struct drm_device *dev)

static void g4x_init_clock_gating(struct drm_device *dev)

drivers/gpu/drm/i915/intel_ringbuffer.c

+0 −8
Original line number Original line Diff line number Diff line
@@ -795,14 +795,6 @@ static int chv_init_workarounds(struct intel_engine_cs *ring) 
	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,

	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,

		  STALL_DOP_GATING_DISABLE);

		  STALL_DOP_GATING_DISABLE);





	/* WaDisableDopClockGating:chv (pre-production hw) */

	WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,

		  DOP_CLOCK_GATING_DISABLE);



	/* WaDisableSamplerPowerBypass:chv (pre-production hw) */

	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,

		  GEN8_SAMPLER_POWER_BYPASS_DIS);



	return 0;

	return 0;

}

}