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Commit 3e288786 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Force CL2 off in CHV x1 PHY 



We can choose to leave the display PHY CL2 powerdown up to some hardware
signals, or we can force it. The BXT code forces the nonexistent CL2 in
the x1 PHY to power down. Follow suit on CHV. Maybe it can still save
some extra power by disabling some extra logic in CL1, or something.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarDeepak S <deepak.s@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent ee279218

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -1149,6 +1149,7 @@ enum skl_disp_power_wells { 
#define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ	(3 << 0)



#define CHV_CMN_DW30			0x8178

#define   DPIO_CL2_LDOFUSE_PWRENB	(1 << 6)

#define   DPIO_LRC_BYPASS		(1 << 3)



#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \

drivers/gpu/drm/i915/intel_runtime_pm.c

+9 −0
Original line number Diff line number Diff line
@@ -996,6 +996,15 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 
		tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);

		tmp |= DPIO_DYNPWRDOWNEN_CH1;

		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);

	} else {

		/*

		 * Force the non-existing CL2 off. BXT does this

		 * too, so maybe it saves some power even though

		 * CL2 doesn't exist?

		 */

		tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);

		tmp |= DPIO_CL2_LDOFUSE_PWRENB;

		vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);

	}



	mutex_unlock(&dev_priv->sb_lock);