Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 3dcc1e7f authored by David Howells's avatar David Howells
Browse files

Blackfin: Split PLL code from mach-specific cdef headers 



Split the PLL control code from the Blackfin machine-specific cdef headers so
that the irqflags functions can be renamed without incurring a header loop.

Signed-off-by: default avatarDavid Howells <dhowells@redhat.com>
parent cb655d0f

arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h

+0 −50
Original line number Diff line number Diff line
@@ -1058,54 +1058,4 @@ 
/* These need to be last due to the cdef/linux inter-dependencies */

#include <asm/irq.h>



/* Writing to PLL_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_PLL_CTL(unsigned int val)

{

	unsigned long flags, iwr0, iwr1;



	if (val == bfin_read_PLL_CTL())

		return;



	local_irq_save_hw(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr0 = bfin_read32(SIC_IWR0);

	iwr1 = bfin_read32(SIC_IWR1);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR0, IWR_ENABLE(0));

	bfin_write32(SIC_IWR1, 0);



	bfin_write16(PLL_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR0, iwr0);

	bfin_write32(SIC_IWR1, iwr1);

	local_irq_restore_hw(flags);

}



/* Writing to VR_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_VR_CTL(unsigned int val)

{

	unsigned long flags, iwr0, iwr1;



	if (val == bfin_read_VR_CTL())

		return;



	local_irq_save_hw(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr0 = bfin_read32(SIC_IWR0);

	iwr1 = bfin_read32(SIC_IWR1);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR0, IWR_ENABLE(0));

	bfin_write32(SIC_IWR1, 0);



	bfin_write16(VR_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR0, iwr0);

	bfin_write32(SIC_IWR1, iwr1);

	local_irq_restore_hw(flags);

}



#endif /* _CDEF_BF52X_H */

arch/blackfin/mach-bf518/include/mach/pll.h

0 → 100644
+63 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2008 Analog Devices Inc.

 *

 * Licensed under the GPL-2 or later

 */



#ifndef _MACH_PLL_H

#define _MACH_PLL_H



#include <asm/blackfin.h>

#include <asm/irqflags.h>



/* Writing to PLL_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_PLL_CTL(unsigned int val)

{

	unsigned long flags, iwr0, iwr1;



	if (val == bfin_read_PLL_CTL())

		return;



	local_irq_save_hw(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr0 = bfin_read32(SIC_IWR0);

	iwr1 = bfin_read32(SIC_IWR1);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR0, IWR_ENABLE(0));

	bfin_write32(SIC_IWR1, 0);



	bfin_write16(PLL_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR0, iwr0);

	bfin_write32(SIC_IWR1, iwr1);

	local_irq_restore_hw(flags);

}



/* Writing to VR_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_VR_CTL(unsigned int val)

{

	unsigned long flags, iwr0, iwr1;



	if (val == bfin_read_VR_CTL())

		return;



	local_irq_save_hw(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr0 = bfin_read32(SIC_IWR0);

	iwr1 = bfin_read32(SIC_IWR1);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR0, IWR_ENABLE(0));

	bfin_write32(SIC_IWR1, 0);



	bfin_write16(VR_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR0, iwr0);

	bfin_write32(SIC_IWR1, iwr1);

	local_irq_restore_hw(flags);

}



#endif /* _MACH_PLL_H */

arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h

+0 −50
Original line number Diff line number Diff line
@@ -1110,54 +1110,4 @@ 
/* These need to be last due to the cdef/linux inter-dependencies */

#include <asm/irq.h>



/* Writing to PLL_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_PLL_CTL(unsigned int val)

{

	unsigned long flags, iwr0, iwr1;



	if (val == bfin_read_PLL_CTL())

		return;



	local_irq_save_hw(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr0 = bfin_read32(SIC_IWR0);

	iwr1 = bfin_read32(SIC_IWR1);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR0, IWR_ENABLE(0));

	bfin_write32(SIC_IWR1, 0);



	bfin_write16(PLL_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR0, iwr0);

	bfin_write32(SIC_IWR1, iwr1);

	local_irq_restore_hw(flags);

}



/* Writing to VR_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_VR_CTL(unsigned int val)

{

	unsigned long flags, iwr0, iwr1;



	if (val == bfin_read_VR_CTL())

		return;



	local_irq_save_hw(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr0 = bfin_read32(SIC_IWR0);

	iwr1 = bfin_read32(SIC_IWR1);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR0, IWR_ENABLE(0));

	bfin_write32(SIC_IWR1, 0);



	bfin_write16(VR_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR0, iwr0);

	bfin_write32(SIC_IWR1, iwr1);

	local_irq_restore_hw(flags);

}



#endif /* _CDEF_BF52X_H */

arch/blackfin/mach-bf527/include/mach/pll.h

0 → 100644
+63 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2007-2008 Analog Devices Inc.

 *

 * Licensed under the GPL-2 or later

 */



#ifndef _MACH_PLL_H

#define _MACH_PLL_H



#include <asm/blackfin.h>

#include <asm/irqflags.h>



/* Writing to PLL_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_PLL_CTL(unsigned int val)

{

	unsigned long flags, iwr0, iwr1;



	if (val == bfin_read_PLL_CTL())

		return;



	local_irq_save_hw(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr0 = bfin_read32(SIC_IWR0);

	iwr1 = bfin_read32(SIC_IWR1);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR0, IWR_ENABLE(0));

	bfin_write32(SIC_IWR1, 0);



	bfin_write16(PLL_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR0, iwr0);

	bfin_write32(SIC_IWR1, iwr1);

	local_irq_restore_hw(flags);

}



/* Writing to VR_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_VR_CTL(unsigned int val)

{

	unsigned long flags, iwr0, iwr1;



	if (val == bfin_read_VR_CTL())

		return;



	local_irq_save_hw(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr0 = bfin_read32(SIC_IWR0);

	iwr1 = bfin_read32(SIC_IWR1);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR0, IWR_ENABLE(0));

	bfin_write32(SIC_IWR1, 0);



	bfin_write16(VR_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR0, iwr0);

	bfin_write32(SIC_IWR1, iwr1);

	local_irq_restore_hw(flags);

}



#endif /* _MACH_PLL_H */

arch/blackfin/mach-bf533/include/mach/cdefBF532.h

+0 −44
Original line number Diff line number Diff line
@@ -697,48 +697,4 @@ BFIN_READ_FIO_FLAG(T) 
#define bfin_read_FIO_FLAG_D()               bfin_read16(FIO_FLAG_D)

#endif



/* Writing to PLL_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_PLL_CTL(unsigned int val)

{

	unsigned long flags, iwr;



	if (val == bfin_read_PLL_CTL())

		return;



	local_irq_save_hw(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr = bfin_read32(SIC_IWR);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR, IWR_ENABLE(0));



	bfin_write16(PLL_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR, iwr);

	local_irq_restore_hw(flags);

}



/* Writing to VR_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_VR_CTL(unsigned int val)

{

	unsigned long flags, iwr;



	if (val == bfin_read_VR_CTL())

		return;



	local_irq_save_hw(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr = bfin_read32(SIC_IWR);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR, IWR_ENABLE(0));



	bfin_write16(VR_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR, iwr);

	local_irq_restore_hw(flags);

}



#endif				/* _CDEF_BF532_H */