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Commit 3ca5da43 authored by Damien Lespiau's avatar Damien Lespiau Committed by Daniel Vetter
Browse files

drm/i915/skl: Implement WaDisableDgMirrorFixInHalfSliceChicken5:skl 



Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 91e41d16

drivers/gpu/drm/i915/i915_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -5866,6 +5866,9 @@ enum punit_power_well { 
#define   GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE	(1<<10)

#define   GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE	(1<<3)



#define GEN9_HALF_SLICE_CHICKEN5	0xe188

#define   GEN9_DG_MIRROR_FIX_ENABLE	(1<<5)



#define GEN8_ROW_CHICKEN		0xe4f0

#define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1<<8)

#define   STALL_DOP_GATING_DISABLE		(1<<5)

drivers/gpu/drm/i915/intel_pm.c

+8 −0
Original line number Diff line number Diff line
@@ -77,6 +77,14 @@ static void gen9_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |

		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);



	/*

	 * WaDisableDgMirrorFixInHalfSliceChicken5:skl

	 * This is a pre-production w/a.

	 */

	I915_WRITE(GEN9_HALF_SLICE_CHICKEN5,

		   I915_READ(GEN9_HALF_SLICE_CHICKEN5) &

		   ~GEN9_DG_MIRROR_FIX_ENABLE);



	/* Wa4x4STCOptimizationDisable:skl */

	I915_WRITE(CACHE_MODE_1,

		   _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));