Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 3c8cdf9b authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Power Context register is only available for gen4 mobiles 



The ability to save the hardware context upon powering down the render
clock through PWRCTXA is only available on a couple of gen4 chipsets.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 88f23b8f

drivers/gpu/drm/i915/intel_display.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -5973,7 +5973,7 @@ void intel_init_clock_gating(struct drm_device *dev) 
				       "Disable RC6\n");

				       "Disable RC6\n");

	}

	}





	if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {

	if (IS_GEN4(dev) && IS_MOBILE(dev)) {

		if (dev_priv->pwrctx == NULL)

		if (dev_priv->pwrctx == NULL)

			dev_priv->pwrctx = intel_alloc_context_page(dev);

			dev_priv->pwrctx = intel_alloc_context_page(dev);

		if (dev_priv->pwrctx) {

		if (dev_priv->pwrctx) {