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Commit 3c6847ea authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull irqchip updates from Ingo Molnar:
 "Various irqchip driver updates, plus a genirq core update that allows
  the initial spreading of irqs amonst CPUs without having to do it from
  user-space"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  genirq: Fix null pointer reference in irq_set_affinity_hint()
  irqchip: gic: Allow interrupt level to be set for PPIs
  irqchip: mips-gic: Handle pending interrupts once in __gic_irq_dispatch()
  irqchip: Conexant CX92755 interrupts controller driver
  irqchip: Devicetree: document Conexant Digicolor irq binding
  irqchip: omap-intc: Remove unused legacy interface for omap2
  irqchip: omap-intc: Fix support for dm814 and dm816
  irqchip: mtk-sysirq: Get irq number from register resource size
  irqchip: renesas-intc-irqpin: r8a7779 IRLM setup support
  genirq: Set initial affinity in irq_set_affinity_hint()
parents 37507717 4fe7ffb7

Documentation/devicetree/bindings/arm/gic.txt

+6 −2
Original line number Diff line number Diff line
@@ -32,12 +32,16 @@ Main node required properties: 
  The 3rd cell is the flags, encoded as follows:

	bits[3:0] trigger type and level flags.

		1 = low-to-high edge triggered

		2 = high-to-low edge triggered

		2 = high-to-low edge triggered (invalid for SPIs)

		4 = active high level-sensitive

		8 = active low level-sensitive

		8 = active low level-sensitive (invalid for SPIs).

	bits[15:8] PPI interrupt cpu mask.  Each bit corresponds to each of

	the 8 possible cpus attached to the GIC.  A bit set to '1' indicated

	the interrupt is wired to that CPU.  Only valid for PPI interrupts.

	Also note that the configurability of PPI interrupts is IMPLEMENTATION

	DEFINED and as such not guaranteed to be present (most SoC available

	in 2014 seem to ignore the setting of this flag and use the hardware

	default value).



- reg : Specifies base physical address(s) and size of the GIC registers. The

  first region is the GIC distributor register base and size. The 2nd region is

Documentation/devicetree/bindings/interrupt-controller/digicolor-ic.txt

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+21 −0
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Conexant Digicolor Interrupt Controller



Required properties:



- compatible : should be "cnxt,cx92755-ic"

- reg : Specifies base physical address and size of the interrupt controller

  registers (IC) area

- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode an

  interrupt source. The value shall be 1.

- syscon: A phandle to the syscon node describing UC registers



Example:



	intc: interrupt-controller@f0000040 {

		compatible = "cnxt,cx92755-ic";

		interrupt-controller;

		#interrupt-cells = <1>;

		reg = <0xf0000040 0x40>;

		syscon = <&uc_regs>;

	};

Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt

+5 −0
Original line number Diff line number Diff line
@@ -9,6 +9,11 @@ Required properties: 
    - "renesas,intc-irqpin-r8a7778" (R-Car M1A)

    - "renesas,intc-irqpin-r8a7779" (R-Car H1)

    - "renesas,intc-irqpin-sh73a0" (SH-Mobile AG5)



- reg: Base address and length of each register bank used by the external

  IRQ pins driven by the interrupt controller hardware module. The base

  addresses, length and number of required register banks varies with soctype.



- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in

  interrupts.txt in this directory

Documentation/devicetree/bindings/interrupt-controller/ti,omap-intc-irq.txt

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+28 −0
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Omap2/3 intc controller



On TI omap2 and 3 the intc interrupt controller can provide

96 or 128 IRQ signals to the ARM host depending on the SoC.



Required Properties:

- compatible: should be one of

			"ti,omap2-intc"

			"ti,omap3-intc"

			"ti,dm814-intc"

			"ti,dm816-intc"

			"ti,am33xx-intc"



- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode interrupt

		     source, should be 1 for intc

- interrupts: interrupt reference to primary interrupt controller



Please refer to interrupts.txt in this directory for details of the common

Interrupt Controllers bindings used by client devices.



Example:

	intc: interrupt-controller@48200000 {

		compatible = "ti,omap3-intc";

		interrupt-controller;

		#interrupt-cells = <1>;

		reg = <0x48200000 0x1000>;

	};

drivers/irqchip/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -42,3 +42,4 @@ obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o 
obj-$(CONFIG_KEYSTONE_IRQ)		+= irq-keystone.o

obj-$(CONFIG_MIPS_GIC)			+= irq-mips-gic.o

obj-$(CONFIG_ARCH_MEDIATEK)		+= irq-mtk-sysirq.o

obj-$(CONFIG_ARCH_DIGICOLOR)		+= irq-digicolor.o