Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 3c52f4eb authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Make adjusted_mode.clock non-pixel multiplied 



It would be easier if adjusted_mode.clock would be the pipe pixel clock,
and it actually is, except for the cases where pixel_multiplier > 1.

So let's change intel_sdvo to use port_clock as the multiplied clock,
and then we can leave adjusted_mode.clock as pipe pixel clock.

v2: Improve port_clock documentation
    Rebased on top of SDVO pixel_multiplier fixes

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 1041a02f

drivers/gpu/drm/i915/intel_display.c

+3 −4
Original line number Diff line number Diff line
@@ -4061,7 +4061,6 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, 
	link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;



	fdi_dotclock = adjusted_mode->clock;

	fdi_dotclock /= pipe_config->pixel_multiplier;



	lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,

					   pipe_config->pipe_bpp);
@@ -7370,8 +7369,7 @@ static void ironlake_crtc_clock_get(struct intel_crtc *crtc, 
	clock = ((u64)link_m * (u64)link_freq);

	do_div(clock, link_n);



	pipe_config->adjusted_mode.clock = clock *

		pipe_config->pixel_multiplier;

	pipe_config->adjusted_mode.clock = clock;

}



/** Returns the currently programmed mode of the given pipe. */
@@ -8316,7 +8314,8 @@ intel_modeset_pipe_config(struct drm_crtc *crtc, 
	/* Set default port clock if not overwritten by the encoder. Needs to be

	 * done afterwards in case the encoder adjusts the mode. */

	if (!pipe_config->port_clock)

		pipe_config->port_clock = pipe_config->adjusted_mode.clock;

		pipe_config->port_clock = pipe_config->adjusted_mode.clock *

			pipe_config->pixel_multiplier;



	ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);

	if (ret < 0) {

drivers/gpu/drm/i915/intel_drv.h

+4 −1
Original line number Diff line number Diff line
@@ -212,6 +212,8 @@ struct intel_crtc_config { 
	unsigned long quirks;



	struct drm_display_mode requested_mode;

	/* Actual pipe timings ie. what we program into the pipe timing

	 * registers. adjusted_mode.clock is the pipe pixel clock. */

	struct drm_display_mode adjusted_mode;

	/* Whether to set up the PCH/FDI. Note that we never allow sharing

	 * between pch encoders and cpu encoders. */
@@ -266,7 +268,8 @@ struct intel_crtc_config { 


	/*

	 * Frequence the dpll for the port should run at. Differs from the

	 * adjusted dotclock e.g. for DP or 12bpc hdmi mode.

	 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also

	 * already multiplied by pixel_multiplier.

	 */

	int port_clock;

drivers/gpu/drm/i915/intel_sdvo.c

+1 −3
Original line number Diff line number Diff line
@@ -1059,7 +1059,7 @@ intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, 


static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_config *pipe_config)

{

	unsigned dotclock = pipe_config->adjusted_mode.clock;

	unsigned dotclock = pipe_config->port_clock;

	struct dpll *clock = &pipe_config->dpll;



	/* SDVO TV has fixed PLL values depend on its clock range,
@@ -1124,7 +1124,6 @@ static bool intel_sdvo_compute_config(struct intel_encoder *encoder, 
	 */

	pipe_config->pixel_multiplier =

		intel_sdvo_get_pixel_multiplier(adjusted_mode);

	adjusted_mode->clock *= pipe_config->pixel_multiplier;



	if (intel_sdvo->color_range_auto) {

		/* See CEA-861-E - 5.1 Default Encoding Parameters */
@@ -1209,7 +1208,6 @@ static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder) 
		return;



	intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);

	input_dtd.part1.clock /= crtc->config.pixel_multiplier;



	if (intel_sdvo->is_tv || intel_sdvo->is_lvds)

		input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;