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Commit 3ad26e5c authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt
Browse files

Merge branch 'for-kvm' into next 



Topic branch for commits that the KVM tree might want to pull
in separately.

Hand merged a few files due to conflicts with the LE stuff

Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
parents 5293bf97 18461960

arch/powerpc/include/asm/machdep.h

+12 −0
Original line number Diff line number Diff line
@@ -78,6 +78,18 @@ struct machdep_calls { 
				    long index);

	void		(*tce_flush)(struct iommu_table *tbl);



	/* _rm versions are for real mode use only */

	int		(*tce_build_rm)(struct iommu_table *tbl,

				     long index,

				     long npages,

				     unsigned long uaddr,

				     enum dma_data_direction direction,

				     struct dma_attrs *attrs);

	void		(*tce_free_rm)(struct iommu_table *tbl,

				    long index,

				    long npages);

	void		(*tce_flush_rm)(struct iommu_table *tbl);



	void __iomem *	(*ioremap)(phys_addr_t addr, unsigned long size,

				   unsigned long flags, void *caller);

	void		(*iounmap)(volatile void __iomem *token);

arch/powerpc/include/asm/pgtable-ppc64.h

+2 −0
Original line number Diff line number Diff line
@@ -394,6 +394,8 @@ static inline void mark_hpte_slot_valid(unsigned char *hpte_slot_array, 
	hpte_slot_array[index] = hidx << 4 | 0x1 << 3;

}



struct page *realmode_pfn_to_page(unsigned long pfn);



static inline char *get_hpte_slot_array(pmd_t *pmdp)

{

	/*

arch/powerpc/include/asm/ppc_asm.h

+6 −91
Original line number Diff line number Diff line
@@ -98,88 +98,32 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR) 
#define REST_8GPRS(n, base)	REST_4GPRS(n, base); REST_4GPRS(n+4, base)

#define REST_10GPRS(n, base)	REST_8GPRS(n, base); REST_2GPRS(n+8, base)



#define SAVE_FPR(n, base)	stfd	n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)

#define SAVE_FPR(n, base)	stfd	n,8*TS_FPRWIDTH*(n)(base)

#define SAVE_2FPRS(n, base)	SAVE_FPR(n, base); SAVE_FPR(n+1, base)

#define SAVE_4FPRS(n, base)	SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)

#define SAVE_8FPRS(n, base)	SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)

#define SAVE_16FPRS(n, base)	SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)

#define SAVE_32FPRS(n, base)	SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)

#define REST_FPR(n, base)	lfd	n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)

#define REST_FPR(n, base)	lfd	n,8*TS_FPRWIDTH*(n)(base)

#define REST_2FPRS(n, base)	REST_FPR(n, base); REST_FPR(n+1, base)

#define REST_4FPRS(n, base)	REST_2FPRS(n, base); REST_2FPRS(n+2, base)

#define REST_8FPRS(n, base)	REST_4FPRS(n, base); REST_4FPRS(n+4, base)

#define REST_16FPRS(n, base)	REST_8FPRS(n, base); REST_8FPRS(n+8, base)

#define REST_32FPRS(n, base)	REST_16FPRS(n, base); REST_16FPRS(n+16, base)



#define SAVE_VR(n,b,base)	li b,THREAD_VR0+(16*(n));  stvx n,base,b

#define SAVE_VR(n,b,base)	li b,16*(n);  stvx n,base,b

#define SAVE_2VRS(n,b,base)	SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)

#define SAVE_4VRS(n,b,base)	SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)

#define SAVE_8VRS(n,b,base)	SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)

#define SAVE_16VRS(n,b,base)	SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)

#define SAVE_32VRS(n,b,base)	SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)

#define REST_VR(n,b,base)	li b,THREAD_VR0+(16*(n)); lvx n,base,b

#define REST_VR(n,b,base)	li b,16*(n); lvx n,base,b

#define REST_2VRS(n,b,base)	REST_VR(n,b,base); REST_VR(n+1,b,base)

#define REST_4VRS(n,b,base)	REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)

#define REST_8VRS(n,b,base)	REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)

#define REST_16VRS(n,b,base)	REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)

#define REST_32VRS(n,b,base)	REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)



/* Save/restore FPRs, VRs and VSRs from their checkpointed backups in

 * thread_struct:

 */

#define SAVE_FPR_TRANSACT(n, base)	stfd n,THREAD_TRANSACT_FPR0+	\

					8*TS_FPRWIDTH*(n)(base)

#define SAVE_2FPRS_TRANSACT(n, base)	SAVE_FPR_TRANSACT(n, base);	\

					SAVE_FPR_TRANSACT(n+1, base)

#define SAVE_4FPRS_TRANSACT(n, base)	SAVE_2FPRS_TRANSACT(n, base);	\

					SAVE_2FPRS_TRANSACT(n+2, base)

#define SAVE_8FPRS_TRANSACT(n, base)	SAVE_4FPRS_TRANSACT(n, base);	\

					SAVE_4FPRS_TRANSACT(n+4, base)

#define SAVE_16FPRS_TRANSACT(n, base)	SAVE_8FPRS_TRANSACT(n, base);	\

					SAVE_8FPRS_TRANSACT(n+8, base)

#define SAVE_32FPRS_TRANSACT(n, base)	SAVE_16FPRS_TRANSACT(n, base);	\

					SAVE_16FPRS_TRANSACT(n+16, base)



#define REST_FPR_TRANSACT(n, base)	lfd	n,THREAD_TRANSACT_FPR0+	\

					8*TS_FPRWIDTH*(n)(base)

#define REST_2FPRS_TRANSACT(n, base)	REST_FPR_TRANSACT(n, base);	\

					REST_FPR_TRANSACT(n+1, base)

#define REST_4FPRS_TRANSACT(n, base)	REST_2FPRS_TRANSACT(n, base);	\

					REST_2FPRS_TRANSACT(n+2, base)

#define REST_8FPRS_TRANSACT(n, base)	REST_4FPRS_TRANSACT(n, base);	\

					REST_4FPRS_TRANSACT(n+4, base)

#define REST_16FPRS_TRANSACT(n, base)	REST_8FPRS_TRANSACT(n, base);	\

					REST_8FPRS_TRANSACT(n+8, base)

#define REST_32FPRS_TRANSACT(n, base)	REST_16FPRS_TRANSACT(n, base);	\

					REST_16FPRS_TRANSACT(n+16, base)





#define SAVE_VR_TRANSACT(n,b,base)	li b,THREAD_TRANSACT_VR0+(16*(n)); \

					stvx n,b,base

#define SAVE_2VRS_TRANSACT(n,b,base)	SAVE_VR_TRANSACT(n,b,base);	\

					SAVE_VR_TRANSACT(n+1,b,base)

#define SAVE_4VRS_TRANSACT(n,b,base)	SAVE_2VRS_TRANSACT(n,b,base);	\

					SAVE_2VRS_TRANSACT(n+2,b,base)

#define SAVE_8VRS_TRANSACT(n,b,base)	SAVE_4VRS_TRANSACT(n,b,base);	\

					SAVE_4VRS_TRANSACT(n+4,b,base)

#define SAVE_16VRS_TRANSACT(n,b,base)	SAVE_8VRS_TRANSACT(n,b,base);	\

					SAVE_8VRS_TRANSACT(n+8,b,base)

#define SAVE_32VRS_TRANSACT(n,b,base)	SAVE_16VRS_TRANSACT(n,b,base);	\

					SAVE_16VRS_TRANSACT(n+16,b,base)



#define REST_VR_TRANSACT(n,b,base)	li b,THREAD_TRANSACT_VR0+(16*(n)); \

					lvx n,b,base

#define REST_2VRS_TRANSACT(n,b,base)	REST_VR_TRANSACT(n,b,base);	\

					REST_VR_TRANSACT(n+1,b,base)

#define REST_4VRS_TRANSACT(n,b,base)	REST_2VRS_TRANSACT(n,b,base);	\

					REST_2VRS_TRANSACT(n+2,b,base)

#define REST_8VRS_TRANSACT(n,b,base)	REST_4VRS_TRANSACT(n,b,base);	\

					REST_4VRS_TRANSACT(n+4,b,base)

#define REST_16VRS_TRANSACT(n,b,base)	REST_8VRS_TRANSACT(n,b,base);	\

					REST_8VRS_TRANSACT(n+8,b,base)

#define REST_32VRS_TRANSACT(n,b,base)	REST_16VRS_TRANSACT(n,b,base);	\

					REST_16VRS_TRANSACT(n+16,b,base)



#ifdef __BIG_ENDIAN__

#define STXVD2X_ROT(n,b,base)		STXVD2X(n,b,base)

#define LXVD2X_ROT(n,b,base)		LXVD2X(n,b,base)
@@ -191,43 +135,14 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR) 
#define LXVD2X_ROT(n,b,base)		LXVD2X(n,b,base);	\

					XXSWAPD(n,n)

#endif



#define SAVE_VSR_TRANSACT(n,b,base)	li b,THREAD_TRANSACT_VSR0+(16*(n)); \

					STXVD2X_ROT(n,R##base,R##b)

#define SAVE_2VSRS_TRANSACT(n,b,base)	SAVE_VSR_TRANSACT(n,b,base);	\

	                                SAVE_VSR_TRANSACT(n+1,b,base)

#define SAVE_4VSRS_TRANSACT(n,b,base)	SAVE_2VSRS_TRANSACT(n,b,base);	\

	                                SAVE_2VSRS_TRANSACT(n+2,b,base)

#define SAVE_8VSRS_TRANSACT(n,b,base)	SAVE_4VSRS_TRANSACT(n,b,base);	\

	                                SAVE_4VSRS_TRANSACT(n+4,b,base)

#define SAVE_16VSRS_TRANSACT(n,b,base)	SAVE_8VSRS_TRANSACT(n,b,base);	\

	                                SAVE_8VSRS_TRANSACT(n+8,b,base)

#define SAVE_32VSRS_TRANSACT(n,b,base)	SAVE_16VSRS_TRANSACT(n,b,base);	\

	                                SAVE_16VSRS_TRANSACT(n+16,b,base)



#define REST_VSR_TRANSACT(n,b,base)	li b,THREAD_TRANSACT_VSR0+(16*(n)); \

					LXVD2X_ROT(n,R##base,R##b)

#define REST_2VSRS_TRANSACT(n,b,base)	REST_VSR_TRANSACT(n,b,base);    \

	                                REST_VSR_TRANSACT(n+1,b,base)

#define REST_4VSRS_TRANSACT(n,b,base)	REST_2VSRS_TRANSACT(n,b,base);	\

	                                REST_2VSRS_TRANSACT(n+2,b,base)

#define REST_8VSRS_TRANSACT(n,b,base)	REST_4VSRS_TRANSACT(n,b,base);	\

	                                REST_4VSRS_TRANSACT(n+4,b,base)

#define REST_16VSRS_TRANSACT(n,b,base)	REST_8VSRS_TRANSACT(n,b,base);	\

	                                REST_8VSRS_TRANSACT(n+8,b,base)

#define REST_32VSRS_TRANSACT(n,b,base)	REST_16VSRS_TRANSACT(n,b,base);	\

	                                REST_16VSRS_TRANSACT(n+16,b,base)



/* Save the lower 32 VSRs in the thread VSR region */

#define SAVE_VSR(n,b,base)	li b,THREAD_VSR0+(16*(n)); \

				STXVD2X_ROT(n,R##base,R##b)

#define SAVE_VSR(n,b,base)	li b,16*(n);  STXVD2X_ROT(n,R##base,R##b)

#define SAVE_2VSRS(n,b,base)	SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)

#define SAVE_4VSRS(n,b,base)	SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)

#define SAVE_8VSRS(n,b,base)	SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)

#define SAVE_16VSRS(n,b,base)	SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)

#define SAVE_32VSRS(n,b,base)	SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)

#define REST_VSR(n,b,base)	li b,THREAD_VSR0+(16*(n)); \

				LXVD2X_ROT(n,R##base,R##b)

#define REST_VSR(n,b,base)	li b,16*(n); LXVD2X_ROT(n,R##base,R##b)

#define REST_2VSRS(n,b,base)	REST_VSR(n,b,base); REST_VSR(n+1,b,base)

#define REST_4VSRS(n,b,base)	REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)

#define REST_8VSRS(n,b,base)	REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)

arch/powerpc/include/asm/processor.h

+25 −22
Original line number Diff line number Diff line
@@ -152,8 +152,20 @@ typedef struct { 
	unsigned long seg;

} mm_segment_t;



#define TS_FPR(i) fpr[i][TS_FPROFFSET]

#define TS_TRANS_FPR(i) transact_fpr[i][TS_FPROFFSET]

#define TS_FPR(i) fp_state.fpr[i][TS_FPROFFSET]

#define TS_TRANS_FPR(i) transact_fp.fpr[i][TS_FPROFFSET]



/* FP and VSX 0-31 register set */

struct thread_fp_state {

	u64	fpr[32][TS_FPRWIDTH] __attribute__((aligned(16)));

	u64	fpscr;		/* Floating point status */

};



/* Complete AltiVec register set including VSCR */

struct thread_vr_state {

	vector128	vr[32] __attribute__((aligned(16)));

	vector128	vscr __attribute__((aligned(16)));

};



struct thread_struct {

	unsigned long	ksp;		/* Kernel stack pointer */
@@ -206,13 +218,8 @@ struct thread_struct { 
	unsigned long	dvc2;

#endif

#endif

	/* FP and VSX 0-31 register set */

	double		fpr[32][TS_FPRWIDTH] __attribute__((aligned(16)));

	struct {



		unsigned int pad;

		unsigned int val;	/* Floating point status */

	} fpscr;

	struct thread_fp_state	fp_state;

	struct thread_fp_state	*fp_save_area;

	int		fpexc_mode;	/* floating-point exception mode */

	unsigned int	align_ctl;	/* alignment handling control */

#ifdef CONFIG_PPC64
@@ -230,10 +237,8 @@ struct thread_struct { 
	struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */

	unsigned long	trap_nr;	/* last trap # on this thread */

#ifdef CONFIG_ALTIVEC

	/* Complete AltiVec register set */

	vector128	vr[32] __attribute__((aligned(16)));

	/* AltiVec status */

	vector128	vscr __attribute__((aligned(16)));

	struct thread_vr_state vr_state;

	struct thread_vr_state *vr_save_area;

	unsigned long	vrsave;

	int		used_vr;	/* set if process has used altivec */

#endif /* CONFIG_ALTIVEC */
@@ -270,13 +275,8 @@ struct thread_struct { 
	 * transact_fpr[] is the new set of transactional values.

	 * VRs work the same way.

	 */

	double		transact_fpr[32][TS_FPRWIDTH];

	struct {

		unsigned int pad;

		unsigned int val;	/* Floating point status */

	} transact_fpscr;

	vector128	transact_vr[32] __attribute__((aligned(16)));

	vector128	transact_vscr __attribute__((aligned(16)));

	struct thread_fp_state transact_fp;

	struct thread_vr_state transact_vr;

	unsigned long	transact_vrsave;

#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */

#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
@@ -330,8 +330,6 @@ struct thread_struct { 
	.ksp = INIT_SP, \

	.regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \

	.fs = KERNEL_DS, \

	.fpr = {{0}}, \

	.fpscr = { .val = 0, }, \

	.fpexc_mode = 0, \

	.ppr = INIT_PPR, \

}
@@ -369,6 +367,11 @@ extern int set_endian(struct task_struct *tsk, unsigned int val); 
extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);

extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);



extern void load_fp_state(struct thread_fp_state *fp);

extern void store_fp_state(struct thread_fp_state *fp);

extern void load_vr_state(struct thread_vr_state *vr);

extern void store_vr_state(struct thread_vr_state *vr);



static inline unsigned int __unpack_fe01(unsigned long msr_bits)

{

	return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);

arch/powerpc/include/asm/sfp-machine.h

+1 −1
Original line number Diff line number Diff line
@@ -125,7 +125,7 @@ 
#define FP_EX_DIVZERO         (1 << (31 - 5))

#define FP_EX_INEXACT         (1 << (31 - 6))



#define __FPU_FPSCR	(current->thread.fpscr.val)

#define __FPU_FPSCR	(current->thread.fp_state.fpscr)



/* We only actually write to the destination register

 * if exceptions signalled (if any) will not trap.