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Commit 3a928e98 authored by Ley Foon Tan's avatar Ley Foon Tan Committed by Bjorn Helgaas
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PCI: altera: Poll for link up status after retraining the link 



Some PCIe devices take a long time to reach link up state after retrain.
Poll for link up status after retraining the link.  This is to make sure
the link is up before we access configuration space.

[bhelgaas: changelog]
Signed-off-by: default avatarLey Foon Tan <lftan@altera.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent c622032e

drivers/pci/host/pcie-altera.c

+11 −1
Original line number Diff line number Diff line
@@ -61,6 +61,8 @@ 
#define TLP_LOOP			500

#define RP_DEVFN			0



#define LINK_UP_TIMEOUT			5000



#define INTX_NUM			4



#define DWORD_MASK			3
@@ -101,6 +103,7 @@ static void altera_pcie_retrain(struct pci_dev *dev) 
{

	u16 linkcap, linkstat;

	struct altera_pcie *pcie = dev->bus->sysdata;

	int timeout =  0;



	if (!altera_pcie_link_is_up(pcie))

		return;
@@ -115,9 +118,16 @@ static void altera_pcie_retrain(struct pci_dev *dev) 
		return;



	pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &linkstat);

	if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB)

	if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {

		pcie_capability_set_word(dev, PCI_EXP_LNKCTL,

					 PCI_EXP_LNKCTL_RL);

		while (!altera_pcie_link_is_up(pcie)) {

			timeout++;

			if (timeout > LINK_UP_TIMEOUT)

				break;

			udelay(5);

		}

	}

}

DECLARE_PCI_FIXUP_EARLY(0x1172, PCI_ANY_ID, altera_pcie_retrain);