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Commit 3a45b05c authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Preserve current RPS frequency across init 



Select idle frequency during initialisation, then reset the last known
frequency when re-enabling. This allows us to preserve the user selected
frequency across resets.

v2: Stop CHV from overriding the user's choice in cherryview_enable_rps()

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1468397438-21226-2-git-send-email-chris@chris-wilson.co.uk
parent b913b33c

drivers/gpu/drm/i915/intel_pm.c

+20 −26
Original line number Diff line number Diff line
@@ -5149,6 +5149,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv) 
	}



	dev_priv->rps.idle_freq = dev_priv->rps.min_freq;

	dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;



	/* Preserve min/max settings in case of re-init */

	if (dev_priv->rps.max_freq_softlimit == 0)
@@ -5165,6 +5166,18 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv) 
	}

}



static void reset_rps(struct drm_i915_private *dev_priv,

		      void (*set)(struct drm_i915_private *, u8))

{

	u8 freq = dev_priv->rps.cur_freq;



	/* force a reset */

	dev_priv->rps.power = -1;

	dev_priv->rps.cur_freq = -1;



	set(dev_priv, freq);

}



/* See the Gen9_GT_PM_Programming_Guide doc for the below */

static void gen9_enable_rps(struct drm_i915_private *dev_priv)

{
@@ -5201,8 +5214,7 @@ static void gen9_enable_rps(struct drm_i915_private *dev_priv) 
	/* Leaning on the below call to gen6_set_rps to program/setup the

	 * Up/Down EI & threshold registers, as well as the RP_CONTROL,

	 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */

	dev_priv->rps.power = HIGH_POWER; /* force a reset */

	gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);

	reset_rps(dev_priv, gen6_set_rps);



	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

}
@@ -5348,8 +5360,7 @@ static void gen8_enable_rps(struct drm_i915_private *dev_priv) 


	/* 6: Ring frequency + overclocking (our driver does this later */



	dev_priv->rps.power = HIGH_POWER; /* force a reset */

	gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);

	reset_rps(dev_priv, gen6_set_rps);



	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

}
@@ -5442,8 +5453,7 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv) 
		dev_priv->rps.max_freq = pcu_mbox & 0xff;

	}



	dev_priv->rps.power = HIGH_POWER; /* force a reset */

	gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);

	reset_rps(dev_priv, gen6_set_rps);



	rc6vids = 0;

	ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
@@ -5807,6 +5817,7 @@ static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv) 
			 dev_priv->rps.min_freq);



	dev_priv->rps.idle_freq = dev_priv->rps.min_freq;

	dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;



	/* Preserve min/max settings in case of re-init */

	if (dev_priv->rps.max_freq_softlimit == 0)
@@ -5871,6 +5882,7 @@ static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv) 
		  "Odd GPU freq values\n");



	dev_priv->rps.idle_freq = dev_priv->rps.min_freq;

	dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;



	/* Preserve min/max settings in case of re-init */

	if (dev_priv->rps.max_freq_softlimit == 0)
@@ -5970,16 +5982,7 @@ static void cherryview_enable_rps(struct drm_i915_private *dev_priv) 
	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));

	DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);



	dev_priv->rps.cur_freq = (val >> 8) & 0xff;

	DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",

			 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),

			 dev_priv->rps.cur_freq);



	DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",

			 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),

			 dev_priv->rps.idle_freq);



	valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);

	reset_rps(dev_priv, valleyview_set_rps);



	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

}
@@ -6059,16 +6062,7 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv) 
	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));

	DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);



	dev_priv->rps.cur_freq = (val >> 8) & 0xff;

	DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",

			 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),

			 dev_priv->rps.cur_freq);



	DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",

			 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),

			 dev_priv->rps.idle_freq);



	valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);

	reset_rps(dev_priv, valleyview_set_rps);



	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

}