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Commit 39c41df9 authored by Soren Brinkmann's avatar Soren Brinkmann Committed by Michal Simek
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arm: zynq: dt: Set correct L2 ram latencies 



Signed-off-by: default avatarSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
parent d4e4ab86

arch/arm/boot/dts/zynq-7000.dtsi

+2 −2
Original line number Original line Diff line number Diff line
@@ -41,8 +41,8 @@ 
		L2: cache-controller {

		L2: cache-controller {

			compatible = "arm,pl310-cache";

			compatible = "arm,pl310-cache";

			reg = <0xF8F02000 0x1000>;

			reg = <0xF8F02000 0x1000>;

			arm,data-latency = <2 3 2>;

			arm,data-latency = <3 2 2>;

			arm,tag-latency = <2 3 2>;

			arm,tag-latency = <2 2 2>;

			cache-unified;

			cache-unified;

			cache-level = <2>;

			cache-level = <2>;

		};

		};