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Commit 3971cdc2 authored by Vineet Gupta's avatar Vineet Gupta
Browse files

ARC: boot: Support Halt-on-reset and Run-on-reset SMP booting modes 



For Run-on-reset, non masters need to spin wait. For Halt-on-reset they
can jump to entry point directly.

Also while at it, made reset vector handler as "the" entry point for
kernel including host debugger based boot (which uses the ELF header
entry point)

Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
parent f33e9c43

arch/arc/Kconfig

+10 −0
Original line number Diff line number Diff line
@@ -194,6 +194,16 @@ config NR_CPUS 
	range 2 4096

	default "4"



config ARC_SMP_HALT_ON_RESET

	bool "Enable Halt-on-reset boot mode"

	default y if ARC_UBOOT_SUPPORT

	help

	  In SMP configuration cores can be configured as Halt-on-reset

	  or they could all start at same time. For Halt-on-reset, non

	  masters are parked until Master kicks them so they can start of

	  at designated entry point. For other case, all jump to common

	  entry point and spin wait for Master's signal.



endif	#SMP



menuconfig ARC_CACHE

arch/arc/kernel/entry-arcv2.S

+1 −1
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ 
	.align 4



# Initial 16 slots are Exception Vectors

VECTOR	stext			; Restart Vector (jump to entry point)

VECTOR	res_service		; Reset Vector

VECTOR	mem_service		; Mem exception

VECTOR	instr_service		; Instrn Error

VECTOR	EV_MachineCheck		; Fatal Machine check

arch/arc/kernel/entry-compact.S

+3 −7
Original line number Diff line number Diff line
@@ -86,7 +86,7 @@ 
 */



; ********* Critical System Events **********************

VECTOR   res_service             ; 0x0, Restart Vector  (0x0)

VECTOR   res_service             ; 0x0, Reset Vector	(0x0)

VECTOR   mem_service             ; 0x8, Mem exception   (0x1)

VECTOR   instr_service           ; 0x10, Instrn Error   (0x2)
@@ -155,13 +155,9 @@ int2_saved_reg: 
; ---------------------------------------------

	.section .text, "ax",@progbits



res_service:		; processor restart

	flag    0x1     ; not implemented

	nop

	nop



reserved:		; processor restart

	rtie            ; jump to processor initializations

reserved:

	flag 1		; Unexpected event, halt



;##################### Interrupt Handling ##############################

arch/arc/kernel/head.S

+27 −20
Original line number Diff line number Diff line
@@ -50,28 +50,37 @@ 
.endm



	.section .init.text, "ax",@progbits

	.type stext, @function

	.globl stext

stext:

	;-------------------------------------------------------------------

	; Don't clobber r0-r2 yet. It might have bootloader provided info

	;-------------------------------------------------------------------



;----------------------------------------------------------------

; Default Reset Handler (jumped into from Reset vector)

; - Don't clobber r0,r1,r2 as they might have u-boot provided args

; - Platforms can override this weak version if needed

;----------------------------------------------------------------

WEAK(res_service)

	j	stext

END(res_service)



;----------------------------------------------------------------

; Kernel Entry point

;----------------------------------------------------------------

ENTRY(stext)



	CPU_EARLY_SETUP



#ifdef CONFIG_SMP

	; Ensure Boot (Master) proceeds. Others wait in platform dependent way

	;	IDENTITY Reg [ 3  2  1  0 ]

	;	(cpu-id)             ^^^	=> Zero for UP ARC700

	;					=> #Core-ID if SMP (Master 0)

	; Note that non-boot CPUs might not land here if halt-on-reset and

	; instead breath life from @first_lines_of_secondary, but we still

	; need to make sure only boot cpu takes this path.

	GET_CPU_ID  r5

	cmp	r5, 0

	mov.ne	r0, r5

	jne	arc_platform_smp_wait_to_boot

	mov.nz	r0, r5

#ifdef CONFIG_ARC_SMP_HALT_ON_RESET

	; Non-Master can proceed as system would be booted sufficiently

	jnz	first_lines_of_secondary

#else

	; Non-Masters wait for Master to boot enough and bring them up

	jnz	arc_platform_smp_wait_to_boot

#endif

	; Master falls thru

#endif



	; Clear BSS before updating any globals

	; XXX: use ZOL here

	mov	r5, __bss_start
@@ -102,16 +111,14 @@ stext: 
	GET_TSK_STACK_BASE r9, sp	; r9 = tsk, sp = stack base(output)



	j	start_kernel	; "C" entry point

END(stext)



#ifdef CONFIG_SMP

;----------------------------------------------------------------

;     First lines of code run by secondary before jumping to 'C'

;----------------------------------------------------------------

	.section .text, "ax",@progbits

	.type first_lines_of_secondary, @function

	.globl first_lines_of_secondary



first_lines_of_secondary:

ENTRY(first_lines_of_secondary)



	CPU_EARLY_SETUP
@@ -126,5 +133,5 @@ first_lines_of_secondary: 
	GET_TSK_STACK_BASE r0, sp



	j	start_kernel_secondary



END(first_lines_of_secondary)

#endif

arch/arc/kernel/vmlinux.lds.S

+1 −1
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@ 
#include <asm/thread_info.h>



OUTPUT_ARCH(arc)

ENTRY(_stext)

ENTRY(res_service)



#ifdef CONFIG_CPU_BIG_ENDIAN

jiffies = jiffies_64 + 4;