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Commit 393538e6 authored by Catalin Marinas's avatar Catalin Marinas
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RealView: Move more device address definitions to board-eb.h



The upcoming PB11MPCore and PB1176 have different memory maps and some
of the definitions in platform.h are no longer common. This patch
moves them to the board-eb.h file and updates their usage in
realview_eb.c.

Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>

parent 9a386f06
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+21 −21
Original line number Diff line number Diff line
@@ -136,12 +136,12 @@ static void __init realview_eb_map_io(void)
/*
 * These devices are connected directly to the multi-layer AHB switch
 */
#define SMC_IRQ		{ NO_IRQ, NO_IRQ }
#define SMC_DMA		{ 0, 0 }
#define EB_SMC_IRQ	{ NO_IRQ, NO_IRQ }
#define EB_SMC_DMA	{ 0, 0 }
#define MPMC_IRQ	{ NO_IRQ, NO_IRQ }
#define MPMC_DMA	{ 0, 0 }
#define CLCD_IRQ	{ IRQ_EB_CLCD, NO_IRQ }
#define CLCD_DMA	{ 0, 0 }
#define EB_CLCD_IRQ	{ IRQ_EB_CLCD, NO_IRQ }
#define EB_CLCD_DMA	{ 0, 0 }
#define DMAC_IRQ	{ IRQ_EB_DMA, NO_IRQ }
#define DMAC_DMA	{ 0, 0 }

@@ -150,14 +150,14 @@ static void __init realview_eb_map_io(void)
 */
#define SCTL_IRQ	{ NO_IRQ, NO_IRQ }
#define SCTL_DMA	{ 0, 0 }
#define WATCHDOG_IRQ	{ IRQ_EB_WDOG, NO_IRQ }
#define WATCHDOG_DMA	{ 0, 0 }
#define GPIO0_IRQ	{ IRQ_EB_GPIO0, NO_IRQ }
#define GPIO0_DMA	{ 0, 0 }
#define EB_WATCHDOG_IRQ	{ IRQ_EB_WDOG, NO_IRQ }
#define EB_WATCHDOG_DMA	{ 0, 0 }
#define EB_GPIO0_IRQ	{ IRQ_EB_GPIO0, NO_IRQ }
#define EB_GPIO0_DMA	{ 0, 0 }
#define GPIO1_IRQ	{ IRQ_EB_GPIO1, NO_IRQ }
#define GPIO1_DMA	{ 0, 0 }
#define RTC_IRQ		{ IRQ_EB_RTC, NO_IRQ }
#define RTC_DMA		{ 0, 0 }
#define EB_RTC_IRQ	{ IRQ_EB_RTC, NO_IRQ }
#define EB_RTC_DMA	{ 0, 0 }

/*
 * These devices are connected via the DMA APB bridge
@@ -172,8 +172,8 @@ static void __init realview_eb_map_io(void)
#define EB_UART2_DMA	{ 11, 10 }
#define EB_UART3_IRQ	{ IRQ_EB_UART3, NO_IRQ }
#define EB_UART3_DMA	{ 0x86, 0x87 }
#define SSP_IRQ		{ IRQ_EB_SSP, NO_IRQ }
#define SSP_DMA		{ 9, 8 }
#define EB_SSP_IRQ	{ IRQ_EB_SSP, NO_IRQ }
#define EB_SSP_DMA	{ 9, 8 }

/* FPGA Primecells */
AMBA_DEVICE(aaci,  "fpga:04", AACI,     NULL);
@@ -183,20 +183,20 @@ AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
AMBA_DEVICE(uart3, "fpga:09", EB_UART3, NULL);

/* DevChip Primecells */
AMBA_DEVICE(smc,   "dev:00",  SMC,      NULL);
AMBA_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
AMBA_DEVICE(smc,   "dev:00",  EB_SMC,   NULL);
AMBA_DEVICE(clcd,  "dev:20",  EB_CLCD,  &clcd_plat_data);
AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
AMBA_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    NULL);
AMBA_DEVICE(wdog,  "dev:e1",  EB_WATCHDOG, NULL);
AMBA_DEVICE(gpio0, "dev:e4",  EB_GPIO0, NULL);
AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    NULL);
AMBA_DEVICE(gpio2, "dev:e6",  GPIO2,    NULL);
AMBA_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
AMBA_DEVICE(rtc,   "dev:e8",  EB_RTC,   NULL);
AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
AMBA_DEVICE(uart0, "dev:f1",  EB_UART0, NULL);
AMBA_DEVICE(uart1, "dev:f2",  EB_UART1, NULL);
AMBA_DEVICE(uart2, "dev:f3",  EB_UART2, NULL);
AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      NULL);
AMBA_DEVICE(ssp0,  "dev:f4",  EB_SSP,   NULL);

static struct amba_device *amba_devs[] __initdata = {
	&dmac_device,
@@ -231,8 +231,8 @@ static struct resource realview_eb_flash_resource = {

static struct resource realview_eb_eth_resources[] = {
	[0] = {
		.start		= REALVIEW_ETH_BASE,
		.end		= REALVIEW_ETH_BASE + SZ_64K - 1,
		.start		= REALVIEW_EB_ETH_BASE,
		.end		= REALVIEW_EB_ETH_BASE + SZ_64K - 1,
		.flags		= IORESOURCE_MEM,
	},
	[1] = {
@@ -254,7 +254,7 @@ static struct platform_device realview_eb_eth_device = {
 */
static int eth_device_register(void)
{
	void __iomem *eth_addr = ioremap(REALVIEW_ETH_BASE, SZ_4K);
	void __iomem *eth_addr = ioremap(REALVIEW_EB_ETH_BASE, SZ_4K);
	u32 idrev;

	if (!eth_addr)
+8 −0
Original line number Diff line number Diff line
@@ -30,13 +30,21 @@
#define REALVIEW_EB_UART1_BASE		0x1000A000	/* UART 1 */
#define REALVIEW_EB_UART2_BASE		0x1000B000	/* UART 2 */
#define REALVIEW_EB_UART3_BASE		0x1000C000	/* UART 3 */
#define REALVIEW_EB_SSP_BASE		0x1000D000	/* Synchronous Serial Port */
#define REALVIEW_EB_WATCHDOG_BASE	0x10010000	/* watchdog interface */
#define REALVIEW_EB_TIMER0_1_BASE	0x10011000	/* Timer 0 and 1 */
#define REALVIEW_EB_TIMER2_3_BASE	0x10012000	/* Timer 2 and 3 */
#define REALVIEW_EB_GPIO0_BASE		0x10013000	/* GPIO port 0 */
#define REALVIEW_EB_RTC_BASE		0x10017000	/* Real Time Clock */
#define REALVIEW_EB_CLCD_BASE		0x10020000	/* CLCD */
#define REALVIEW_EB_GIC_CPU_BASE	0x10040000	/* Generic interrupt controller CPU interface */
#define REALVIEW_EB_GIC_DIST_BASE	0x10041000	/* Generic interrupt controller distributor */
#define REALVIEW_EB_SMC_BASE		0x10080000	/* Static memory controller */

#define REALVIEW_EB_FLASH_BASE		0x40000000
#define REALVIEW_EB_FLASH_SIZE		SZ_64M
#define REALVIEW_EB_ETH_BASE		0x4E000000	/* Ethernet */
#define REALVIEW_EB_USB_BASE		0x4F000000	/* USB */

#ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB
#define REALVIEW_EB11MP_SCU_BASE	0x10100000	/* SCU registers */
+1 −15
Original line number Diff line number Diff line
@@ -172,34 +172,20 @@
#define REALVIEW_INTREG_CARDINSERT   0x03    /* Signal insertion of MMC card                   */

/*
 * REALVIEW peripheral addresses
 * RealView common peripheral addresses
 */
#define REALVIEW_SCTL_BASE            0x10001000	/* System controller */
#define REALVIEW_I2C_BASE             0x10002000	/* I2C control */
	/* Reserved 0x10003000 */
#define REALVIEW_AACI_BASE            0x10004000	/* Audio */
#define REALVIEW_MMCI0_BASE           0x10005000	/* MMC interface */
#define REALVIEW_KMI0_BASE            0x10006000	/* KMI interface */
#define REALVIEW_KMI1_BASE            0x10007000	/* KMI 2nd interface */
#define REALVIEW_CHAR_LCD_BASE        0x10008000	/* Character LCD */
#define REALVIEW_SSP_BASE             0x1000D000	/* Synchronous Serial Port */
#define REALVIEW_SCI_BASE             0x1000E000	/* Smart card controller */
	/* Reserved 0x1000F000 */
#define REALVIEW_WATCHDOG_BASE        0x10010000	/* watchdog interface */
#define REALVIEW_GPIO0_BASE           0x10013000	/* GPIO port 0 */
#define REALVIEW_GPIO1_BASE           0x10014000	/* GPIO port 1 */
#define REALVIEW_GPIO2_BASE           0x10015000	/* GPIO port 2 */
	/* Reserved 0x10016000 */
#define REALVIEW_RTC_BASE             0x10017000	/* Real Time Clock */
#define REALVIEW_DMC_BASE             0x10018000	/* DMC configuration */
#define REALVIEW_PCI_CORE_BASE        0x10019000	/* PCI configuration */
	/* Reserved 0x1001A000 - 0x1001FFFF */
#define REALVIEW_CLCD_BASE            0x10020000	/* CLCD */
#define REALVIEW_DMAC_BASE            0x10030000	/* DMA controller */
#define REALVIEW_SMC_BASE             0x10080000	/* SMC */
	/* Reserved 0x10090000 - 0x100EFFFF */

#define REALVIEW_ETH_BASE             0x4E000000	/* Ethernet */

/* PCI space */
#define REALVIEW_PCI_BASE             0x41000000	/* PCI Interface */