Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 386d325d authored by Lendacky, Thomas's avatar Lendacky, Thomas Committed by David S. Miller
Browse files

amd-xgbe: Set DMA mask based on hardware register value 



The hardware supplies a value that indicates the DMA range that it
is capable of using. Use this value rather than hard-coding it in
the driver.

Signed-off-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent ceb8f6be

drivers/net/ethernet/amd/xgbe/xgbe-common.h

+2 −0
Original line number Diff line number Diff line
@@ -365,6 +365,8 @@ 
#define MAC_HWF0R_TXCOESEL_WIDTH	1

#define MAC_HWF0R_VLHASH_INDEX		4

#define MAC_HWF0R_VLHASH_WIDTH		1

#define MAC_HWF1R_ADDR64_INDEX		14

#define MAC_HWF1R_ADDR64_WIDTH		2

#define MAC_HWF1R_ADVTHWORD_INDEX	13

#define MAC_HWF1R_ADVTHWORD_WIDTH	1

#define MAC_HWF1R_DBGMEMA_INDEX		19

drivers/net/ethernet/amd/xgbe/xgbe-drv.c

+16 −0
Original line number Diff line number Diff line
@@ -519,6 +519,7 @@ void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata) 
						RXFIFOSIZE);

	hw_feat->tx_fifo_size  = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,

						TXFIFOSIZE);

	hw_feat->dma_width     = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);

	hw_feat->dcb           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);

	hw_feat->sph           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);

	hw_feat->tso           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
@@ -553,6 +554,21 @@ void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata) 
		break;

	}



	/* Translate the address width setting into actual number */

	switch (hw_feat->dma_width) {

	case 0:

		hw_feat->dma_width = 32;

		break;

	case 1:

		hw_feat->dma_width = 40;

		break;

	case 2:

		hw_feat->dma_width = 48;

		break;

	default:

		hw_feat->dma_width = 32;

	}



	/* The Queue, Channel and TC counts are zero based so increment them

	 * to get the actual number

	 */

drivers/net/ethernet/amd/xgbe/xgbe-main.c

+10 −9
Original line number Diff line number Diff line
@@ -374,15 +374,6 @@ static int xgbe_probe(struct platform_device *pdev) 
		pdata->awcache = XGBE_DMA_SYS_AWCACHE;

	}



	/* Set the DMA mask */

	if (!dev->dma_mask)

		dev->dma_mask = &dev->coherent_dma_mask;

	ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));

	if (ret) {

		dev_err(dev, "dma_set_mask_and_coherent failed\n");

		goto err_io;

	}



	/* Get the device interrupt */

	ret = platform_get_irq(pdev, 0);

	if (ret < 0) {
@@ -409,6 +400,16 @@ static int xgbe_probe(struct platform_device *pdev) 
	/* Set default configuration data */

	xgbe_default_config(pdata);



	/* Set the DMA mask */

	if (!dev->dma_mask)

		dev->dma_mask = &dev->coherent_dma_mask;

	ret = dma_set_mask_and_coherent(dev,

					DMA_BIT_MASK(pdata->hw_feat.dma_width));

	if (ret) {

		dev_err(dev, "dma_set_mask_and_coherent failed\n");

		goto err_io;

	}



	/* Calculate the number of Tx and Rx rings to be created

	 *  -Tx (DMA) Channels map 1-to-1 to Tx Queues so set

	 *   the number of Tx queues to the number of Tx channels

drivers/net/ethernet/amd/xgbe/xgbe.h

+1 −0
Original line number Diff line number Diff line
@@ -632,6 +632,7 @@ struct xgbe_hw_features { 
	unsigned int rx_fifo_size;	/* MTL Receive FIFO Size */

	unsigned int tx_fifo_size;	/* MTL Transmit FIFO Size */

	unsigned int adv_ts_hi;		/* Advance Timestamping High Word */

	unsigned int dma_width;		/* DMA width */

	unsigned int dcb;		/* DCB Feature */

	unsigned int sph;		/* Split Header Feature */

	unsigned int tso;		/* TCP Segmentation Offload */