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Commit 382b0936 authored by Jesse Barnes's avatar Jesse Barnes Committed by Chris Wilson
Browse files

drm/i915: diasable clock gating for the panel power sequencer 



Needed on Ibex Peak and Cougar Point or the panel won't always come on.

Cc: stable@kernel.org
Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 298b0b39

drivers/gpu/drm/i915/i915_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -2784,6 +2784,9 @@ 
#define  FDI_RX_PHASE_SYNC_POINTER_ENABLE       (1)

#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, FDI_RXA_CHICKEN, FDI_RXB_CHICKEN)



#define SOUTH_DSPCLK_GATE_D	0xc2020

#define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)



/* CPU: FDI_TX */

#define FDI_TXA_CTL             0x60100

#define FDI_TXB_CTL             0x61100

drivers/gpu/drm/i915/intel_display.c

+7 −0
Original line number Diff line number Diff line
@@ -5745,6 +5745,13 @@ void intel_init_clock_gating(struct drm_device *dev) 


		I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);



		/*

		 * On Ibex Peak and Cougar Point, we need to disable clock

		 * gating for the panel power sequencer or it will fail to

		 * start up when no ports are active.

		 */

		I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);



		/*

		 * According to the spec the following bits should be set in

		 * order to enable memory self-refresh