Merge remote-tracking branches 'asoc/topic/intel', 'asoc/topic/kirkwood',... (373e515d) · Commits · e / devices / android_kernel_teracube_2e

sound/soc/codecs/lm49453.c

+1 −5

Original line number	Original line	Diff line number	Diff line
	@@ -188,7 +188,6 @@ static struct reg_default lm49453_reg_defs[] = {
	/* codec private data */		/* codec private data */
	struct lm49453_priv {		struct lm49453_priv {
	struct regmap *regmap;		struct regmap *regmap;
	int fs_rate;
	};		};

	/* capture path controls */		/* capture path controls */
	@@ -1112,13 +1111,10 @@ static int lm49453_hw_params(struct snd_pcm_substream *substream,
	struct snd_soc_dai *dai)		struct snd_soc_dai *dai)
	{		{
	struct snd_soc_codec *codec = dai->codec;		struct snd_soc_codec *codec = dai->codec;
	struct lm49453_priv *lm49453 = snd_soc_codec_get_drvdata(codec);
	u16 clk_div = 0;		u16 clk_div = 0;

	lm49453->fs_rate = params_rate(params);

	/* Setting DAC clock dividers based on substream sample rate. */		/* Setting DAC clock dividers based on substream sample rate. */
	switch (lm49453->fs_rate) {		switch (params_rate(params)) {
	case 8000:		case 8000:
	case 16000:		case 16000:
	case 32000:		case 32000:

sound/soc/codecs/max9768.c

+18 −43

Original line number	Original line	Diff line number	Diff line
	@@ -43,8 +43,8 @@ static struct reg_default max9768_default_regs[] = {
	static int max9768_get_gpio(struct snd_kcontrol *kcontrol,		static int max9768_get_gpio(struct snd_kcontrol *kcontrol,
	struct snd_ctl_elem_value *ucontrol)		struct snd_ctl_elem_value *ucontrol)
	{		{
	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);		struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol);
	struct max9768 *max9768 = snd_soc_codec_get_drvdata(codec);		struct max9768 *max9768 = snd_soc_component_get_drvdata(c);
	int val = gpio_get_value_cansleep(max9768->mute_gpio);		int val = gpio_get_value_cansleep(max9768->mute_gpio);

	ucontrol->value.integer.value[0] = !val;		ucontrol->value.integer.value[0] = !val;
	@@ -55,8 +55,8 @@ static int max9768_get_gpio(struct snd_kcontrol *kcontrol,
	static int max9768_set_gpio(struct snd_kcontrol *kcontrol,		static int max9768_set_gpio(struct snd_kcontrol *kcontrol,
	struct snd_ctl_elem_value *ucontrol)		struct snd_ctl_elem_value *ucontrol)
	{		{
	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);		struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol);
	struct max9768 *max9768 = snd_soc_codec_get_drvdata(codec);		struct max9768 *max9768 = snd_soc_component_get_drvdata(c);

	gpio_set_value_cansleep(max9768->mute_gpio, !ucontrol->value.integer.value[0]);		gpio_set_value_cansleep(max9768->mute_gpio, !ucontrol->value.integer.value[0]);

	@@ -130,19 +130,20 @@ static const struct snd_soc_dapm_route max9768_dapm_routes[] = {
	{ "OUT-", NULL, "IN" },		{ "OUT-", NULL, "IN" },
	};		};

	static int max9768_probe(struct snd_soc_codec *codec)		static int max9768_probe(struct snd_soc_component *component)
	{		{
	struct max9768 *max9768 = snd_soc_codec_get_drvdata(codec);		struct max9768 *max9768 = snd_soc_component_get_drvdata(component);
	int ret;		int ret;

	if (max9768->flags & MAX9768_FLAG_CLASSIC_PWM) {		if (max9768->flags & MAX9768_FLAG_CLASSIC_PWM) {
	ret = snd_soc_write(codec, MAX9768_CTRL, MAX9768_CTRL_PWM);		ret = regmap_write(max9768->regmap, MAX9768_CTRL,
			MAX9768_CTRL_PWM);
	if (ret)		if (ret)
	return ret;		return ret;
	}		}

	if (gpio_is_valid(max9768->mute_gpio)) {		if (gpio_is_valid(max9768->mute_gpio)) {
	ret = snd_soc_add_codec_controls(codec, max9768_mute,		ret = snd_soc_add_component_controls(component, max9768_mute,
	ARRAY_SIZE(max9768_mute));		ARRAY_SIZE(max9768_mute));
	if (ret)		if (ret)
	return ret;		return ret;
	@@ -151,7 +152,7 @@ static int max9768_probe(struct snd_soc_codec *codec)
	return 0;		return 0;
	}		}

	static struct snd_soc_codec_driver max9768_codec_driver = {		static struct snd_soc_component_driver max9768_component_driver = {
	.probe = max9768_probe,		.probe = max9768_probe,
	.controls = max9768_volume,		.controls = max9768_volume,
	.num_controls = ARRAY_SIZE(max9768_volume),		.num_controls = ARRAY_SIZE(max9768_volume),
	@@ -183,11 +184,13 @@ static int max9768_i2c_probe(struct i2c_client *client,

	if (pdata) {		if (pdata) {
	/* Mute on powerup to avoid clicks */		/* Mute on powerup to avoid clicks */
	err = gpio_request_one(pdata->mute_gpio, GPIOF_INIT_HIGH, "MAX9768 Mute");		err = devm_gpio_request_one(&client->dev, pdata->mute_gpio,
			GPIOF_INIT_HIGH, "MAX9768 Mute");
	max9768->mute_gpio = err ?: pdata->mute_gpio;		max9768->mute_gpio = err ?: pdata->mute_gpio;

	/* Activate chip by releasing shutdown, enables I2C */		/* Activate chip by releasing shutdown, enables I2C */
	err = gpio_request_one(pdata->shdn_gpio, GPIOF_INIT_HIGH, "MAX9768 Shutdown");		err = devm_gpio_request_one(&client->dev, pdata->shdn_gpio,
			GPIOF_INIT_HIGH, "MAX9768 Shutdown");
	max9768->shdn_gpio = err ?: pdata->shdn_gpio;		max9768->shdn_gpio = err ?: pdata->shdn_gpio;

	max9768->flags = pdata->flags;		max9768->flags = pdata->flags;
	@@ -199,38 +202,11 @@ static int max9768_i2c_probe(struct i2c_client *client,
	i2c_set_clientdata(client, max9768);		i2c_set_clientdata(client, max9768);

	max9768->regmap = devm_regmap_init_i2c(client, &max9768_i2c_regmap_config);		max9768->regmap = devm_regmap_init_i2c(client, &max9768_i2c_regmap_config);
	if (IS_ERR(max9768->regmap)) {		if (IS_ERR(max9768->regmap))
	err = PTR_ERR(max9768->regmap);		return PTR_ERR(max9768->regmap);
	goto err_gpio_free;
	}

	err = snd_soc_register_codec(&client->dev, &max9768_codec_driver, NULL, 0);
	if (err)
	goto err_gpio_free;

	return 0;

	err_gpio_free:
	if (gpio_is_valid(max9768->shdn_gpio))
	gpio_free(max9768->shdn_gpio);
	if (gpio_is_valid(max9768->mute_gpio))
	gpio_free(max9768->mute_gpio);

	return err;
	}

	static int max9768_i2c_remove(struct i2c_client *client)
	{
	struct max9768 *max9768 = i2c_get_clientdata(client);

	snd_soc_unregister_codec(&client->dev);		return devm_snd_soc_register_component(&client->dev,
			&max9768_component_driver, NULL, 0);
	if (gpio_is_valid(max9768->shdn_gpio))
	gpio_free(max9768->shdn_gpio);
	if (gpio_is_valid(max9768->mute_gpio))
	gpio_free(max9768->mute_gpio);

	return 0;
	}		}

	static const struct i2c_device_id max9768_i2c_id[] = {		static const struct i2c_device_id max9768_i2c_id[] = {
	@@ -244,7 +220,6 @@ static struct i2c_driver max9768_i2c_driver = {
	.name = "max9768",		.name = "max9768",
	},		},
	.probe = max9768_i2c_probe,		.probe = max9768_i2c_probe,
	.remove = max9768_i2c_remove,
	.id_table = max9768_i2c_id,		.id_table = max9768_i2c_id,
	};		};
	module_i2c_driver(max9768_i2c_driver);		module_i2c_driver(max9768_i2c_driver);

sound/soc/codecs/max98088.c

+25 −280

Original line number	Original line	Diff line number	Diff line
	@@ -258,292 +258,36 @@ static const struct reg_default max98088_reg[] = {
	{ 0xc9, 0x00 }, /* C9 DAI2 biquad */		{ 0xc9, 0x00 }, /* C9 DAI2 biquad */
	};		};

	static struct {
	int readable;
	int writable;
	int vol;
	} max98088_access[M98088_REG_CNT] = {
	{ 0xFF, 0xFF, 1 }, /* 00 IRQ status */
	{ 0xFF, 0x00, 1 }, /* 01 MIC status */
	{ 0xFF, 0x00, 1 }, /* 02 jack status */
	{ 0x1F, 0x1F, 1 }, /* 03 battery voltage */
	{ 0xFF, 0xFF, 0 }, /* 04 */
	{ 0xFF, 0xFF, 0 }, /* 05 */
	{ 0xFF, 0xFF, 0 }, /* 06 */
	{ 0xFF, 0xFF, 0 }, /* 07 */
	{ 0xFF, 0xFF, 0 }, /* 08 */
	{ 0xFF, 0xFF, 0 }, /* 09 */
	{ 0xFF, 0xFF, 0 }, /* 0A */
	{ 0xFF, 0xFF, 0 }, /* 0B */
	{ 0xFF, 0xFF, 0 }, /* 0C */
	{ 0xFF, 0xFF, 0 }, /* 0D */
	{ 0xFF, 0xFF, 0 }, /* 0E */
	{ 0xFF, 0xFF, 0 }, /* 0F interrupt enable */

	{ 0xFF, 0xFF, 0 }, /* 10 master clock */
	{ 0xFF, 0xFF, 0 }, /* 11 DAI1 clock mode */
	{ 0xFF, 0xFF, 0 }, /* 12 DAI1 clock control */
	{ 0xFF, 0xFF, 0 }, /* 13 DAI1 clock control */
	{ 0xFF, 0xFF, 0 }, /* 14 DAI1 format */
	{ 0xFF, 0xFF, 0 }, /* 15 DAI1 clock */
	{ 0xFF, 0xFF, 0 }, /* 16 DAI1 config */
	{ 0xFF, 0xFF, 0 }, /* 17 DAI1 TDM */
	{ 0xFF, 0xFF, 0 }, /* 18 DAI1 filters */
	{ 0xFF, 0xFF, 0 }, /* 19 DAI2 clock mode */
	{ 0xFF, 0xFF, 0 }, /* 1A DAI2 clock control */
	{ 0xFF, 0xFF, 0 }, /* 1B DAI2 clock control */
	{ 0xFF, 0xFF, 0 }, /* 1C DAI2 format */
	{ 0xFF, 0xFF, 0 }, /* 1D DAI2 clock */
	{ 0xFF, 0xFF, 0 }, /* 1E DAI2 config */
	{ 0xFF, 0xFF, 0 }, /* 1F DAI2 TDM */

	{ 0xFF, 0xFF, 0 }, /* 20 DAI2 filters */
	{ 0xFF, 0xFF, 0 }, /* 21 data config */
	{ 0xFF, 0xFF, 0 }, /* 22 DAC mixer */
	{ 0xFF, 0xFF, 0 }, /* 23 left ADC mixer */
	{ 0xFF, 0xFF, 0 }, /* 24 right ADC mixer */
	{ 0xFF, 0xFF, 0 }, /* 25 left HP mixer */
	{ 0xFF, 0xFF, 0 }, /* 26 right HP mixer */
	{ 0xFF, 0xFF, 0 }, /* 27 HP control */
	{ 0xFF, 0xFF, 0 }, /* 28 left REC mixer */
	{ 0xFF, 0xFF, 0 }, /* 29 right REC mixer */
	{ 0xFF, 0xFF, 0 }, /* 2A REC control */
	{ 0xFF, 0xFF, 0 }, /* 2B left SPK mixer */
	{ 0xFF, 0xFF, 0 }, /* 2C right SPK mixer */
	{ 0xFF, 0xFF, 0 }, /* 2D SPK control */
	{ 0xFF, 0xFF, 0 }, /* 2E sidetone */
	{ 0xFF, 0xFF, 0 }, /* 2F DAI1 playback level */

	{ 0xFF, 0xFF, 0 }, /* 30 DAI1 playback level */
	{ 0xFF, 0xFF, 0 }, /* 31 DAI2 playback level */
	{ 0xFF, 0xFF, 0 }, /* 32 DAI2 playbakc level */
	{ 0xFF, 0xFF, 0 }, /* 33 left ADC level */
	{ 0xFF, 0xFF, 0 }, /* 34 right ADC level */
	{ 0xFF, 0xFF, 0 }, /* 35 MIC1 level */
	{ 0xFF, 0xFF, 0 }, /* 36 MIC2 level */
	{ 0xFF, 0xFF, 0 }, /* 37 INA level */
	{ 0xFF, 0xFF, 0 }, /* 38 INB level */
	{ 0xFF, 0xFF, 0 }, /* 39 left HP volume */
	{ 0xFF, 0xFF, 0 }, /* 3A right HP volume */
	{ 0xFF, 0xFF, 0 }, /* 3B left REC volume */
	{ 0xFF, 0xFF, 0 }, /* 3C right REC volume */
	{ 0xFF, 0xFF, 0 }, /* 3D left SPK volume */
	{ 0xFF, 0xFF, 0 }, /* 3E right SPK volume */
	{ 0xFF, 0xFF, 0 }, /* 3F MIC config */

	{ 0xFF, 0xFF, 0 }, /* 40 MIC threshold */
	{ 0xFF, 0xFF, 0 }, /* 41 excursion limiter filter */
	{ 0xFF, 0xFF, 0 }, /* 42 excursion limiter threshold */
	{ 0xFF, 0xFF, 0 }, /* 43 ALC */
	{ 0xFF, 0xFF, 0 }, /* 44 power limiter threshold */
	{ 0xFF, 0xFF, 0 }, /* 45 power limiter config */
	{ 0xFF, 0xFF, 0 }, /* 46 distortion limiter config */
	{ 0xFF, 0xFF, 0 }, /* 47 audio input */
	{ 0xFF, 0xFF, 0 }, /* 48 microphone */
	{ 0xFF, 0xFF, 0 }, /* 49 level control */
	{ 0xFF, 0xFF, 0 }, /* 4A bypass switches */
	{ 0xFF, 0xFF, 0 }, /* 4B jack detect */
	{ 0xFF, 0xFF, 0 }, /* 4C input enable */
	{ 0xFF, 0xFF, 0 }, /* 4D output enable */
	{ 0xFF, 0xFF, 0 }, /* 4E bias control */
	{ 0xFF, 0xFF, 0 }, /* 4F DAC power */

	{ 0xFF, 0xFF, 0 }, /* 50 DAC power */
	{ 0xFF, 0xFF, 0 }, /* 51 system */
	{ 0xFF, 0xFF, 0 }, /* 52 DAI1 EQ1 */
	{ 0xFF, 0xFF, 0 }, /* 53 DAI1 EQ1 */
	{ 0xFF, 0xFF, 0 }, /* 54 DAI1 EQ1 */
	{ 0xFF, 0xFF, 0 }, /* 55 DAI1 EQ1 */
	{ 0xFF, 0xFF, 0 }, /* 56 DAI1 EQ1 */
	{ 0xFF, 0xFF, 0 }, /* 57 DAI1 EQ1 */
	{ 0xFF, 0xFF, 0 }, /* 58 DAI1 EQ1 */
	{ 0xFF, 0xFF, 0 }, /* 59 DAI1 EQ1 */
	{ 0xFF, 0xFF, 0 }, /* 5A DAI1 EQ1 */
	{ 0xFF, 0xFF, 0 }, /* 5B DAI1 EQ1 */
	{ 0xFF, 0xFF, 0 }, /* 5C DAI1 EQ2 */
	{ 0xFF, 0xFF, 0 }, /* 5D DAI1 EQ2 */
	{ 0xFF, 0xFF, 0 }, /* 5E DAI1 EQ2 */
	{ 0xFF, 0xFF, 0 }, /* 5F DAI1 EQ2 */

	{ 0xFF, 0xFF, 0 }, /* 60 DAI1 EQ2 */
	{ 0xFF, 0xFF, 0 }, /* 61 DAI1 EQ2 */
	{ 0xFF, 0xFF, 0 }, /* 62 DAI1 EQ2 */
	{ 0xFF, 0xFF, 0 }, /* 63 DAI1 EQ2 */
	{ 0xFF, 0xFF, 0 }, /* 64 DAI1 EQ2 */
	{ 0xFF, 0xFF, 0 }, /* 65 DAI1 EQ2 */
	{ 0xFF, 0xFF, 0 }, /* 66 DAI1 EQ3 */
	{ 0xFF, 0xFF, 0 }, /* 67 DAI1 EQ3 */
	{ 0xFF, 0xFF, 0 }, /* 68 DAI1 EQ3 */
	{ 0xFF, 0xFF, 0 }, /* 69 DAI1 EQ3 */
	{ 0xFF, 0xFF, 0 }, /* 6A DAI1 EQ3 */
	{ 0xFF, 0xFF, 0 }, /* 6B DAI1 EQ3 */
	{ 0xFF, 0xFF, 0 }, /* 6C DAI1 EQ3 */
	{ 0xFF, 0xFF, 0 }, /* 6D DAI1 EQ3 */
	{ 0xFF, 0xFF, 0 }, /* 6E DAI1 EQ3 */
	{ 0xFF, 0xFF, 0 }, /* 6F DAI1 EQ3 */

	{ 0xFF, 0xFF, 0 }, /* 70 DAI1 EQ4 */
	{ 0xFF, 0xFF, 0 }, /* 71 DAI1 EQ4 */
	{ 0xFF, 0xFF, 0 }, /* 72 DAI1 EQ4 */
	{ 0xFF, 0xFF, 0 }, /* 73 DAI1 EQ4 */
	{ 0xFF, 0xFF, 0 }, /* 74 DAI1 EQ4 */
	{ 0xFF, 0xFF, 0 }, /* 75 DAI1 EQ4 */
	{ 0xFF, 0xFF, 0 }, /* 76 DAI1 EQ4 */
	{ 0xFF, 0xFF, 0 }, /* 77 DAI1 EQ4 */
	{ 0xFF, 0xFF, 0 }, /* 78 DAI1 EQ4 */
	{ 0xFF, 0xFF, 0 }, /* 79 DAI1 EQ4 */
	{ 0xFF, 0xFF, 0 }, /* 7A DAI1 EQ5 */
	{ 0xFF, 0xFF, 0 }, /* 7B DAI1 EQ5 */
	{ 0xFF, 0xFF, 0 }, /* 7C DAI1 EQ5 */
	{ 0xFF, 0xFF, 0 }, /* 7D DAI1 EQ5 */
	{ 0xFF, 0xFF, 0 }, /* 7E DAI1 EQ5 */
	{ 0xFF, 0xFF, 0 }, /* 7F DAI1 EQ5 */

	{ 0xFF, 0xFF, 0 }, /* 80 DAI1 EQ5 */
	{ 0xFF, 0xFF, 0 }, /* 81 DAI1 EQ5 */
	{ 0xFF, 0xFF, 0 }, /* 82 DAI1 EQ5 */
	{ 0xFF, 0xFF, 0 }, /* 83 DAI1 EQ5 */
	{ 0xFF, 0xFF, 0 }, /* 84 DAI2 EQ1 */
	{ 0xFF, 0xFF, 0 }, /* 85 DAI2 EQ1 */
	{ 0xFF, 0xFF, 0 }, /* 86 DAI2 EQ1 */
	{ 0xFF, 0xFF, 0 }, /* 87 DAI2 EQ1 */
	{ 0xFF, 0xFF, 0 }, /* 88 DAI2 EQ1 */
	{ 0xFF, 0xFF, 0 }, /* 89 DAI2 EQ1 */
	{ 0xFF, 0xFF, 0 }, /* 8A DAI2 EQ1 */
	{ 0xFF, 0xFF, 0 }, /* 8B DAI2 EQ1 */
	{ 0xFF, 0xFF, 0 }, /* 8C DAI2 EQ1 */
	{ 0xFF, 0xFF, 0 }, /* 8D DAI2 EQ1 */
	{ 0xFF, 0xFF, 0 }, /* 8E DAI2 EQ2 */
	{ 0xFF, 0xFF, 0 }, /* 8F DAI2 EQ2 */

	{ 0xFF, 0xFF, 0 }, /* 90 DAI2 EQ2 */
	{ 0xFF, 0xFF, 0 }, /* 91 DAI2 EQ2 */
	{ 0xFF, 0xFF, 0 }, /* 92 DAI2 EQ2 */
	{ 0xFF, 0xFF, 0 }, /* 93 DAI2 EQ2 */
	{ 0xFF, 0xFF, 0 }, /* 94 DAI2 EQ2 */
	{ 0xFF, 0xFF, 0 }, /* 95 DAI2 EQ2 */
	{ 0xFF, 0xFF, 0 }, /* 96 DAI2 EQ2 */
	{ 0xFF, 0xFF, 0 }, /* 97 DAI2 EQ2 */
	{ 0xFF, 0xFF, 0 }, /* 98 DAI2 EQ3 */
	{ 0xFF, 0xFF, 0 }, /* 99 DAI2 EQ3 */
	{ 0xFF, 0xFF, 0 }, /* 9A DAI2 EQ3 */
	{ 0xFF, 0xFF, 0 }, /* 9B DAI2 EQ3 */
	{ 0xFF, 0xFF, 0 }, /* 9C DAI2 EQ3 */
	{ 0xFF, 0xFF, 0 }, /* 9D DAI2 EQ3 */
	{ 0xFF, 0xFF, 0 }, /* 9E DAI2 EQ3 */
	{ 0xFF, 0xFF, 0 }, /* 9F DAI2 EQ3 */

	{ 0xFF, 0xFF, 0 }, /* A0 DAI2 EQ3 */
	{ 0xFF, 0xFF, 0 }, /* A1 DAI2 EQ3 */
	{ 0xFF, 0xFF, 0 }, /* A2 DAI2 EQ4 */
	{ 0xFF, 0xFF, 0 }, /* A3 DAI2 EQ4 */
	{ 0xFF, 0xFF, 0 }, /* A4 DAI2 EQ4 */
	{ 0xFF, 0xFF, 0 }, /* A5 DAI2 EQ4 */
	{ 0xFF, 0xFF, 0 }, /* A6 DAI2 EQ4 */
	{ 0xFF, 0xFF, 0 }, /* A7 DAI2 EQ4 */
	{ 0xFF, 0xFF, 0 }, /* A8 DAI2 EQ4 */
	{ 0xFF, 0xFF, 0 }, /* A9 DAI2 EQ4 */
	{ 0xFF, 0xFF, 0 }, /* AA DAI2 EQ4 */
	{ 0xFF, 0xFF, 0 }, /* AB DAI2 EQ4 */
	{ 0xFF, 0xFF, 0 }, /* AC DAI2 EQ5 */
	{ 0xFF, 0xFF, 0 }, /* AD DAI2 EQ5 */
	{ 0xFF, 0xFF, 0 }, /* AE DAI2 EQ5 */
	{ 0xFF, 0xFF, 0 }, /* AF DAI2 EQ5 */

	{ 0xFF, 0xFF, 0 }, /* B0 DAI2 EQ5 */
	{ 0xFF, 0xFF, 0 }, /* B1 DAI2 EQ5 */
	{ 0xFF, 0xFF, 0 }, /* B2 DAI2 EQ5 */
	{ 0xFF, 0xFF, 0 }, /* B3 DAI2 EQ5 */
	{ 0xFF, 0xFF, 0 }, /* B4 DAI2 EQ5 */
	{ 0xFF, 0xFF, 0 }, /* B5 DAI2 EQ5 */
	{ 0xFF, 0xFF, 0 }, /* B6 DAI1 biquad */
	{ 0xFF, 0xFF, 0 }, /* B7 DAI1 biquad */
	{ 0xFF, 0xFF, 0 }, /* B8 DAI1 biquad */
	{ 0xFF, 0xFF, 0 }, /* B9 DAI1 biquad */
	{ 0xFF, 0xFF, 0 }, /* BA DAI1 biquad */
	{ 0xFF, 0xFF, 0 }, /* BB DAI1 biquad */
	{ 0xFF, 0xFF, 0 }, /* BC DAI1 biquad */
	{ 0xFF, 0xFF, 0 }, /* BD DAI1 biquad */
	{ 0xFF, 0xFF, 0 }, /* BE DAI1 biquad */
	{ 0xFF, 0xFF, 0 }, /* BF DAI1 biquad */

	{ 0xFF, 0xFF, 0 }, /* C0 DAI2 biquad */
	{ 0xFF, 0xFF, 0 }, /* C1 DAI2 biquad */
	{ 0xFF, 0xFF, 0 }, /* C2 DAI2 biquad */
	{ 0xFF, 0xFF, 0 }, /* C3 DAI2 biquad */
	{ 0xFF, 0xFF, 0 }, /* C4 DAI2 biquad */
	{ 0xFF, 0xFF, 0 }, /* C5 DAI2 biquad */
	{ 0xFF, 0xFF, 0 }, /* C6 DAI2 biquad */
	{ 0xFF, 0xFF, 0 }, /* C7 DAI2 biquad */
	{ 0xFF, 0xFF, 0 }, /* C8 DAI2 biquad */
	{ 0xFF, 0xFF, 0 }, /* C9 DAI2 biquad */
	{ 0x00, 0x00, 0 }, /* CA */
	{ 0x00, 0x00, 0 }, /* CB */
	{ 0x00, 0x00, 0 }, /* CC */
	{ 0x00, 0x00, 0 }, /* CD */
	{ 0x00, 0x00, 0 }, /* CE */
	{ 0x00, 0x00, 0 }, /* CF */

	{ 0x00, 0x00, 0 }, /* D0 */
	{ 0x00, 0x00, 0 }, /* D1 */
	{ 0x00, 0x00, 0 }, /* D2 */
	{ 0x00, 0x00, 0 }, /* D3 */
	{ 0x00, 0x00, 0 }, /* D4 */
	{ 0x00, 0x00, 0 }, /* D5 */
	{ 0x00, 0x00, 0 }, /* D6 */
	{ 0x00, 0x00, 0 }, /* D7 */
	{ 0x00, 0x00, 0 }, /* D8 */
	{ 0x00, 0x00, 0 }, /* D9 */
	{ 0x00, 0x00, 0 }, /* DA */
	{ 0x00, 0x00, 0 }, /* DB */
	{ 0x00, 0x00, 0 }, /* DC */
	{ 0x00, 0x00, 0 }, /* DD */
	{ 0x00, 0x00, 0 }, /* DE */
	{ 0x00, 0x00, 0 }, /* DF */

	{ 0x00, 0x00, 0 }, /* E0 */
	{ 0x00, 0x00, 0 }, /* E1 */
	{ 0x00, 0x00, 0 }, /* E2 */
	{ 0x00, 0x00, 0 }, /* E3 */
	{ 0x00, 0x00, 0 }, /* E4 */
	{ 0x00, 0x00, 0 }, /* E5 */
	{ 0x00, 0x00, 0 }, /* E6 */
	{ 0x00, 0x00, 0 }, /* E7 */
	{ 0x00, 0x00, 0 }, /* E8 */
	{ 0x00, 0x00, 0 }, /* E9 */
	{ 0x00, 0x00, 0 }, /* EA */
	{ 0x00, 0x00, 0 }, /* EB */
	{ 0x00, 0x00, 0 }, /* EC */
	{ 0x00, 0x00, 0 }, /* ED */
	{ 0x00, 0x00, 0 }, /* EE */
	{ 0x00, 0x00, 0 }, /* EF */

	{ 0x00, 0x00, 0 }, /* F0 */
	{ 0x00, 0x00, 0 }, /* F1 */
	{ 0x00, 0x00, 0 }, /* F2 */
	{ 0x00, 0x00, 0 }, /* F3 */
	{ 0x00, 0x00, 0 }, /* F4 */
	{ 0x00, 0x00, 0 }, /* F5 */
	{ 0x00, 0x00, 0 }, /* F6 */
	{ 0x00, 0x00, 0 }, /* F7 */
	{ 0x00, 0x00, 0 }, /* F8 */
	{ 0x00, 0x00, 0 }, /* F9 */
	{ 0x00, 0x00, 0 }, /* FA */
	{ 0x00, 0x00, 0 }, /* FB */
	{ 0x00, 0x00, 0 }, /* FC */
	{ 0x00, 0x00, 0 }, /* FD */
	{ 0x00, 0x00, 0 }, /* FE */
	{ 0xFF, 0x00, 1 }, /* FF */
	};

	static bool max98088_readable_register(struct device *dev, unsigned int reg)		static bool max98088_readable_register(struct device *dev, unsigned int reg)
	{		{
	return max98088_access[reg].readable;		switch (reg) {
			case M98088_REG_00_IRQ_STATUS ... 0xC9:
			case M98088_REG_FF_REV_ID:
			return true;
			default:
			return false;
			}
			}

			static bool max98088_writeable_register(struct device *dev, unsigned int reg)
			{
			switch (reg) {
			case M98088_REG_03_BATTERY_VOLTAGE ... 0xC9:
			return true;
			default:
			return false;
			}
	}		}

	static bool max98088_volatile_register(struct device *dev, unsigned int reg)		static bool max98088_volatile_register(struct device *dev, unsigned int reg)
	{		{
	return max98088_access[reg].vol;		switch (reg) {
			case M98088_REG_00_IRQ_STATUS ... M98088_REG_03_BATTERY_VOLTAGE:
			case M98088_REG_FF_REV_ID:
			return true;
			default:
			return false;
			}
	}		}

	static const struct regmap_config max98088_regmap = {		static const struct regmap_config max98088_regmap = {
	@@ -551,6 +295,7 @@ static const struct regmap_config max98088_regmap = {
	.val_bits = 8,		.val_bits = 8,

	.readable_reg = max98088_readable_register,		.readable_reg = max98088_readable_register,
			.writeable_reg = max98088_writeable_register,
	.volatile_reg = max98088_volatile_register,		.volatile_reg = max98088_volatile_register,
	.max_register = 0xff,		.max_register = 0xff,

sound/soc/codecs/max98088.h

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -16,7 +16,7 @@
	*/		*/
	#define M98088_REG_00_IRQ_STATUS 0x00		#define M98088_REG_00_IRQ_STATUS 0x00
	#define M98088_REG_01_MIC_STATUS 0x01		#define M98088_REG_01_MIC_STATUS 0x01
	#define M98088_REG_02_JACK_STAUS 0x02		#define M98088_REG_02_JACK_STATUS 0x02
	#define M98088_REG_03_BATTERY_VOLTAGE 0x03		#define M98088_REG_03_BATTERY_VOLTAGE 0x03
	#define M98088_REG_0F_IRQ_ENABLE 0x0F		#define M98088_REG_0F_IRQ_ENABLE 0x0F
	#define M98088_REG_10_SYS_CLK 0x10		#define M98088_REG_10_SYS_CLK 0x10

sound/soc/intel/Kconfig

+18 −11

Original line number	Original line	Diff line number	Diff line
	@@ -26,14 +26,9 @@ config SND_SST_IPC_ACPI
	depends on ACPI		depends on ACPI

	config SND_SOC_INTEL_SST		config SND_SOC_INTEL_SST
	tristate "ASoC support for Intel(R) Smart Sound Technology"		tristate
	select SND_SOC_INTEL_SST_ACPI if ACPI		select SND_SOC_INTEL_SST_ACPI if ACPI
	depends on (X86 \|\| COMPILE_TEST)		depends on (X86 \|\| COMPILE_TEST)
	depends on DW_DMAC_CORE
	help
	This adds support for Intel(R) Smart Sound Technology (SST).
	Say Y if you have such a device
	If unsure select "N".

	config SND_SOC_INTEL_SST_ACPI		config SND_SOC_INTEL_SST_ACPI
	tristate		tristate
	@@ -46,8 +41,9 @@ config SND_SOC_INTEL_BAYTRAIL

	config SND_SOC_INTEL_HASWELL_MACH		config SND_SOC_INTEL_HASWELL_MACH
	tristate "ASoC Audio DSP support for Intel Haswell Lynxpoint"		tristate "ASoC Audio DSP support for Intel Haswell Lynxpoint"
	depends on SND_SOC_INTEL_SST && X86_INTEL_LPSS && I2C && \		depends on X86_INTEL_LPSS && I2C && I2C_DESIGNWARE_PLATFORM
	I2C_DESIGNWARE_PLATFORM		depends on DW_DMAC_CORE
			select SND_SOC_INTEL_SST
	select SND_SOC_INTEL_HASWELL		select SND_SOC_INTEL_HASWELL
	select SND_SOC_RT5640		select SND_SOC_RT5640
	help		help
	@@ -58,7 +54,9 @@ config SND_SOC_INTEL_HASWELL_MACH

	config SND_SOC_INTEL_BYT_RT5640_MACH		config SND_SOC_INTEL_BYT_RT5640_MACH
	tristate "ASoC Audio driver for Intel Baytrail with RT5640 codec"		tristate "ASoC Audio driver for Intel Baytrail with RT5640 codec"
	depends on SND_SOC_INTEL_SST && X86_INTEL_LPSS && I2C		depends on X86_INTEL_LPSS && I2C
			depends on DW_DMAC_CORE
			select SND_SOC_INTEL_SST
	select SND_SOC_INTEL_BAYTRAIL		select SND_SOC_INTEL_BAYTRAIL
	select SND_SOC_RT5640		select SND_SOC_RT5640
	help		help
	@@ -67,7 +65,9 @@ config SND_SOC_INTEL_BYT_RT5640_MACH

	config SND_SOC_INTEL_BYT_MAX98090_MACH		config SND_SOC_INTEL_BYT_MAX98090_MACH
	tristate "ASoC Audio driver for Intel Baytrail with MAX98090 codec"		tristate "ASoC Audio driver for Intel Baytrail with MAX98090 codec"
	depends on SND_SOC_INTEL_SST && X86_INTEL_LPSS && I2C		depends on X86_INTEL_LPSS && I2C
			depends on DW_DMAC_CORE
			select SND_SOC_INTEL_SST
	select SND_SOC_INTEL_BAYTRAIL		select SND_SOC_INTEL_BAYTRAIL
	select SND_SOC_MAX98090		select SND_SOC_MAX98090
	help		help
	@@ -76,8 +76,10 @@ config SND_SOC_INTEL_BYT_MAX98090_MACH

	config SND_SOC_INTEL_BROADWELL_MACH		config SND_SOC_INTEL_BROADWELL_MACH
	tristate "ASoC Audio DSP support for Intel Broadwell Wildcatpoint"		tristate "ASoC Audio DSP support for Intel Broadwell Wildcatpoint"
	depends on SND_SOC_INTEL_SST && X86_INTEL_LPSS && DW_DMAC && \		depends on X86_INTEL_LPSS && I2C && DW_DMAC && \
	I2C_DESIGNWARE_PLATFORM		I2C_DESIGNWARE_PLATFORM
			depends on DW_DMAC_CORE
			select SND_SOC_INTEL_SST
	select SND_SOC_INTEL_HASWELL		select SND_SOC_INTEL_HASWELL
	select SND_SOC_RT286		select SND_SOC_RT286
	help		help
	@@ -132,3 +134,8 @@ config SND_SOC_INTEL_CHT_BSW_MAX98090_TI_MACH
	This adds support for ASoC machine driver for Intel(R) Cherrytrail & Braswell		This adds support for ASoC machine driver for Intel(R) Cherrytrail & Braswell
	platforms with MAX98090 audio codec it also can support TI jack chip as aux device.		platforms with MAX98090 audio codec it also can support TI jack chip as aux device.
	If unsure select "N".		If unsure select "N".

			config SND_SOC_INTEL_SKYLAKE
			tristate
			select SND_HDA_EXT_CORE
			select SND_SOC_INTEL_SST