Merge tag 'dmaengine-4.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma

Analog Device AXI-DMAC DMA controller

Required properties:

 - compatible: Must be "adi,axi-dmac-1.00.a".

 - reg: Specification for the controllers memory mapped register map.

 - interrupts: Specification for the controllers interrupt.

 - clocks: Phandle and specifier to the controllers AXI interface clock

 - #dma-cells: Must be 1.

Required sub-nodes:

 - adi,channels: This sub-node must contain a sub-node for each DMA channel. For

   the channel sub-nodes the following bindings apply. They must match the

   configuration options of the peripheral as it was instantiated.

Required properties for adi,channels sub-node:

 - #size-cells: Must be 0

 - #address-cells: Must be 1

Required channel sub-node properties:

 - reg: Which channel this node refers to.

 - adi,length-width: Width of the DMA transfer length register.

 - adi,source-bus-width,

   adi,destination-bus-width: Width of the source or destination bus in bits.

 - adi,source-bus-type,

   adi,destination-bus-type: Type of the source or destination bus. Must be one

   of the following:

	0 (AXI_DMAC_TYPE_AXI_MM): Memory mapped AXI interface

	1 (AXI_DMAC_TYPE_AXI_STREAM): Streaming AXI interface

	2 (AXI_DMAC_TYPE_AXI_FIFO): FIFO interface

Optional channel properties:

 - adi,cyclic: Must be set if the channel supports hardware cyclic DMA

   transfers.

 - adi,2d: Must be set if the channel supports hardware 2D DMA transfers.

DMA clients connected to the AXI-DMAC DMA controller must use the format

described in the dma.txt file using a one-cell specifier. The value of the

specifier refers to the DMA channel index.

Example:

dma: dma@7c420000 {

	compatible = "adi,axi-dmac-1.00.a";

	reg = <0x7c420000 0x10000>;

	interrupts = <0 57 0>;

	clocks = <&clkc 16>;

	#dma-cells = <1>;

	adi,channels {

		#size-cells = <0>;

		#address-cells = <1>;

		dma-channel@0 {

			reg = <0>;

			adi,source-bus-width = <32>;

			adi,source-bus-type = <ADI_AXI_DMAC_TYPE_MM_AXI>;

			adi,destination-bus-width = <64>;

			adi,destination-bus-type = <ADI_AXI_DMAC_TYPE_FIFO>;

		};

	};

};

* ARM PrimeCells PL080 and PL081 and derivatives DMA controller

Required properties:

- compatible: "arm,pl080", "arm,primecell";

	      "arm,pl081", "arm,primecell";

- reg: Address range of the PL08x registers

- interrupt: The PL08x interrupt number

- clocks: The clock running the IP core clock

- clock-names: Must contain "apb_pclk"

- lli-bus-interface-ahb1: if AHB master 1 is eligible for fetching LLIs

- lli-bus-interface-ahb2: if AHB master 2 is eligible for fetching LLIs

- mem-bus-interface-ahb1: if AHB master 1 is eligible for fetching memory contents

- mem-bus-interface-ahb2: if AHB master 2 is eligible for fetching memory contents

- #dma-cells: must be <2>. First cell should contain the DMA request,

              second cell should contain either 1 or 2 depending on

              which AHB master that is used.

Optional properties:

- dma-channels: contains the total number of DMA channels supported by the DMAC

- dma-requests: contains the total number of DMA requests supported by the DMAC

- memcpy-burst-size: the size of the bursts for memcpy: 1, 4, 8, 16, 32

  64, 128 or 256 bytes are legal values

- memcpy-bus-width: the bus width used for memcpy: 8, 16 or 32 are legal

  values

Clients

Required properties:

- dmas: List of DMA controller phandle, request channel and AHB master id

- dma-names: Names of the aforementioned requested channels

Example:

dmac0: dma-controller@10130000 {

	compatible = "arm,pl080", "arm,primecell";

	reg = <0x10130000 0x1000>;

	interrupt-parent = <&vica>;

	interrupts = <15>;

	clocks = <&hclkdma0>;

	clock-names = "apb_pclk";

	lli-bus-interface-ahb1;

	lli-bus-interface-ahb2;

	mem-bus-interface-ahb2;

	memcpy-burst-size = <256>;

	memcpy-bus-width = <32>;

	#dma-cells = <2>;

};

device@40008000 {

	...

	dmas = <&dmac0 0 2

		&dmac0 1 2>;

	dma-names = "tx", "rx";

	...

};

NXP LPC18xx/43xx DMA MUX (DMA request router)

Required properties:

- compatible:	"nxp,lpc1850-dmamux"

- reg:		Memory map for accessing module

- #dma-cells:	Should be set to <3>.

		* 1st cell contain the master dma request signal

		* 2nd cell contain the mux value (0-3) for the peripheral

		* 3rd cell contain either 1 or 2 depending on the AHB

		  master used.

- dma-requests:	Number of DMA requests for the mux

- dma-masters:	phandle pointing to the DMA controller

The DMA controller node need to have the following poroperties:

- dma-requests:	Number of DMA requests the controller can handle

Example:

dmac: dma@40002000 {

	compatible = "nxp,lpc1850-gpdma", "arm,pl080", "arm,primecell";

	arm,primecell-periphid = <0x00041080>;

	reg = <0x40002000 0x1000>;

	interrupts = <2>;

	clocks = <&ccu1 CLK_CPU_DMA>;

	clock-names = "apb_pclk";

	#dma-cells = <2>;

	dma-channels = <8>;

	dma-requests = <16>;

	lli-bus-interface-ahb1;

	lli-bus-interface-ahb2;

	mem-bus-interface-ahb1;

	mem-bus-interface-ahb2;

	memcpy-burst-size = <256>;

	memcpy-bus-width = <32>;

};

dmamux: dma-mux {

	compatible = "nxp,lpc1850-dmamux";

	#dma-cells = <3>;

	dma-requests = <64>;

	dma-masters = <&dmac>;

};

uart0: serial@40081000 {

	compatible = "nxp,lpc1850-uart", "ns16550a";

	reg = <0x40081000 0x1000>;

	reg-shift = <2>;

	interrupts = <24>;

	clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;

	clock-names = "uartclk", "reg";

	dmas = <&dmamux 1 1 2

		&dmamux 2 1 2>;

	dma-names = "tx", "rx";

};

properties:

- interrupts: interrupt of the XOR channel

And the following optional properties:

The sub-nodes used to contain one or several of the following

properties, but they are now deprecated:

- dmacap,memcpy to indicate that the XOR channel is capable of memcpy operations

- dmacap,memset to indicate that the XOR channel is capable of memset operations

- dmacap,xor to indicate that the XOR channel is capable of xor operations

- dmacap,interrupt to indicate that the XOR channel is capable of

  generating interrupts

Example:

	xor00 {

	      interrupts = <51>;

	      dmacap,memcpy;

	      dmacap,xor;

	};

	xor01 {

	      interrupts = <52>;

	      dmacap,memcpy;

	      dmacap,xor;

	      dmacap,memset;

	};

};

Allwinner A10 DMA Controller

This driver follows the generic DMA bindings defined in dma.txt.

Required properties:

- compatible:	Must be "allwinner,sun4i-a10-dma"

- reg:		Should contain the registers base address and length

- interrupts:	Should contain a reference to the interrupt used by this device

- clocks:	Should contain a reference to the parent AHB clock

- #dma-cells :	Should be 2, first cell denoting normal or dedicated dma,

		second cell holding the request line number.

Example:

	dma: dma-controller@01c02000 {

		compatible = "allwinner,sun4i-a10-dma";

		reg = <0x01c02000 0x1000>;

		interrupts = <27>;

		clocks = <&ahb_gates 6>;

		#dma-cells = <2>;

	};

Clients:

DMA clients connected to the Allwinner A10 DMA controller must use the

format described in the dma.txt file, using a three-cell specifier for

each channel: a phandle plus two integer cells.

The three cells in order are:

1. A phandle pointing to the DMA controller.

2. Whether it is using normal (0) or dedicated (1) channels

3. The port ID as specified in the datasheet

Example:

	spi2: spi@01c17000 {

		compatible = "allwinner,sun4i-a10-spi";

		reg = <0x01c17000 0x1000>;

		interrupts = <0 12 4>;

		clocks = <&ahb_gates 22>, <&spi2_clk>;

		clock-names = "ahb", "mod";

		dmas = <&dma 1 29>, <&dma 1 28>;

		dma-names = "rx", "tx";

		status = "disabled";

		#address-cells = <1>;

		#size-cells = <0>;

	};