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Commit 34c510b2 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull MIPS fixes from Ralf Baechle:
 "A set of MIPS fixes for 4.9:

   - lots of fixes for printk continuations
   - six fixes for FP related code.
   - fix max_low_pfn with disabled highmem
   - fix KASLR handling of NULL FDT and KASLR for generic kernels
   - fix build of compressed image
   - provide default mips_cpc_default_phys_base to ignore CPC
   - fix reboot on Malta"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: Fix max_low_pfn with disabled highmem
  MIPS: Correct MIPS I FP sigcontext layout
  MIPS: Fix ISA I/II FP signal context offsets
  MIPS: Remove FIR from ISA I FP signal context
  MIPS: Fix ISA I FP sigcontext access violation handling
  MIPS: Fix FCSR Cause bit handling for correct SIGFPE issue
  MIPS: ptrace: Also initialize the FP context on individual FCSR writes
  MIPS: dump_tlb: Fix printk continuations
  MIPS: Fix __show_regs() output
  MIPS: traps: Fix output of show_code
  MIPS: traps: Fix output of show_stacktrace
  MIPS: traps: Fix output of show_backtrace
  MIPS: Fix build of compressed image
  MIPS: generic: Fix KASLR for generic kernel.
  MIPS: KASLR: Fix handling of NULL FDT
  MIPS: Malta: Fixup reboot
  MIPS: CPC: Provide default mips_cpc_default_phys_base to ignore CPC
parents f7df76e6 16a767ec

arch/mips/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -263,7 +263,7 @@ KBUILD_CPPFLAGS += -DDATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0) 


bootvars-y	= VMLINUX_LOAD_ADDRESS=$(load-y) \

		  VMLINUX_ENTRY_ADDRESS=$(entry-y) \

		  PLATFORM=$(platform-y)

		  PLATFORM="$(platform-y)"

ifdef CONFIG_32BIT

bootvars-y	+= ADDR_BITS=32

endif

arch/mips/boot/dts/mti/malta.dts

+2 −1
Original line number Diff line number Diff line
@@ -84,12 +84,13 @@ 
	fpga_regs: system-controller@1f000000 {

		compatible = "mti,malta-fpga", "syscon", "simple-mfd";

		reg = <0x1f000000 0x1000>;

		native-endian;



		reboot {

			compatible = "syscon-reboot";

			regmap = <&fpga_regs>;

			offset = <0x500>;

			mask = <0x4d>;

			mask = <0x42>;

		};

	};

arch/mips/generic/init.c

+10 −6
Original line number Diff line number Diff line
@@ -29,10 +29,20 @@ static __initdata const struct mips_machine *mach; 
static __initdata const void *mach_match_data;



void __init prom_init(void)

{

	plat_get_fdt();

	BUG_ON(!fdt);

}



void __init *plat_get_fdt(void)

{

	const struct mips_machine *check_mach;

	const struct of_device_id *match;



	if (fdt)

		/* Already set up */

		return (void *)fdt;



	if ((fw_arg0 == -2) && !fdt_check_header((void *)fw_arg1)) {

		/*

		 * We booted using the UHI boot protocol, so we have been
@@ -75,12 +85,6 @@ void __init prom_init(void) 
		/* Retrieve the machine's FDT */

		fdt = mach->fdt;

	}



	BUG_ON(!fdt);

}



void __init *plat_get_fdt(void)

{

	return (void *)fdt;

}

arch/mips/include/asm/fpu_emulator.h

+13 −0
Original line number Diff line number Diff line
@@ -63,6 +63,8 @@ do { \ 
extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,

				    struct mips_fpu_struct *ctx, int has_fpu,

				    void *__user *fault_addr);

void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr,

		     struct task_struct *tsk);

int process_fpemu_return(int sig, void __user *fault_addr,

			 unsigned long fcr31);

int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
@@ -81,4 +83,15 @@ static inline void fpu_emulator_init_fpu(void) 
		set_fpr64(&t->thread.fpu.fpr[i], 0, SIGNALLING_NAN);

}



/*

 * Mask the FCSR Cause bits according to the Enable bits, observing

 * that Unimplemented is always enabled.

 */

static inline unsigned long mask_fcr31_x(unsigned long fcr31)

{

	return fcr31 & (FPU_CSR_UNI_X |

			((fcr31 & FPU_CSR_ALL_E) <<

			 (ffs(FPU_CSR_ALL_X) - ffs(FPU_CSR_ALL_E))));

}



#endif /* _ASM_FPU_EMULATOR_H */

arch/mips/include/asm/switch_to.h

+18 −0
Original line number Diff line number Diff line
@@ -75,6 +75,22 @@ do { if (cpu_has_rw_llb) { \ 
	}								\

} while (0)



/*

 * Check FCSR for any unmasked exceptions pending set with `ptrace',

 * clear them and send a signal.

 */

#define __sanitize_fcr31(next)						\

do {									\

	unsigned long fcr31 = mask_fcr31_x(next->thread.fpu.fcr31);	\

	void __user *pc;						\

									\

	if (unlikely(fcr31)) {						\

		pc = (void __user *)task_pt_regs(next)->cp0_epc;	\

		next->thread.fpu.fcr31 &= ~fcr31;			\

		force_fcr31_sig(fcr31, pc, next);			\

	}								\

} while (0)



/*

 * For newly created kernel threads switch_to() will return to

 * ret_from_kernel_thread, newly created user threads to ret_from_fork.
@@ -85,6 +101,8 @@ do { if (cpu_has_rw_llb) { \ 
do {									\

	__mips_mt_fpaff_switch_to(prev);				\

	lose_fpu_inatomic(1, prev);					\

	if (tsk_used_math(next))					\

		__sanitize_fcr31(next);					\

	if (cpu_has_dsp) {						\

		__save_dsp(prev);					\

		__restore_dsp(next);					\