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Commit 34adb28d authored by Ralf Baechle's avatar Ralf Baechle
Browse files

MIPS: Replace MIPS-specific 64BIT_PHYS_ADDR with generic PHYS_ADDR_T_64BIT 



Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent f9861407

arch/mips/Kconfig

+6 −9
Original line number Diff line number Diff line
@@ -63,7 +63,7 @@ choice 


config MIPS_ALCHEMY

	bool "Alchemy processor based machines"

	select 64BIT_PHYS_ADDR

	select ARCH_PHYS_ADDR_T_64BIT

	select CEVT_R4K

	select CSRC_R4K

	select IRQ_CPU
@@ -771,7 +771,7 @@ config MIKROTIK_RB532 
config CAVIUM_OCTEON_SOC

	bool "Cavium Networks Octeon SoC based boards"

	select CEVT_R4K

	select 64BIT_PHYS_ADDR

	select ARCH_PHYS_ADDR_T_64BIT

	select DMA_COHERENT

	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN
@@ -813,7 +813,7 @@ config NLM_XLR_BOARD 
	select SWAP_IO_SPACE

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_64BIT_KERNEL

	select 64BIT_PHYS_ADDR

	select ARCH_PHYS_ADDR_T_64BIT

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_HIGHMEM

	select DMA_COHERENT
@@ -839,7 +839,7 @@ config NLM_XLP_BOARD 
	select HW_HAS_PCI

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_64BIT_KERNEL

	select 64BIT_PHYS_ADDR

	select ARCH_PHYS_ADDR_T_64BIT

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select SYS_SUPPORTS_HIGHMEM
@@ -979,7 +979,7 @@ config FW_CFE 
	bool



config ARCH_DMA_ADDR_T_64BIT

	def_bool (HIGHMEM && 64BIT_PHYS_ADDR) || 64BIT

	def_bool (HIGHMEM && ARCH_PHYS_ADDR_T_64BIT) || 64BIT



config DMA_MAYBE_COHERENT

	select DMA_NONCOHERENT
@@ -2124,11 +2124,8 @@ config SB1_PASS_2_1_WORKAROUNDS 
	default y





config 64BIT_PHYS_ADDR

	bool



config ARCH_PHYS_ADDR_T_64BIT

       def_bool 64BIT_PHYS_ADDR

       bool



config CPU_HAS_SMARTMIPS

	depends on SYS_SUPPORTS_SMARTMIPS

arch/mips/alchemy/common/setup.c

+1 −1
Original line number Diff line number Diff line
@@ -70,7 +70,7 @@ void __init plat_mem_setup(void) 
	iomem_resource.end = IOMEM_RESOURCE_END;

}



#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_PCI)

#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_PCI)

/* This routine should be valid for all Au1x based boards */

phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)

{

arch/mips/include/asm/mach-au1x00/ioremap.h

+1 −1
Original line number Diff line number Diff line
@@ -11,7 +11,7 @@ 


#include <linux/types.h>



#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_PCI)

#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_PCI)

extern phys_t __fixup_bigphys_addr(phys_t, phys_t);

#else

static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)

arch/mips/include/asm/page.h

+1 −1
Original line number Diff line number Diff line
@@ -116,7 +116,7 @@ extern void copy_user_highpage(struct page *to, struct page *from, 
/*

 * These are used to make use of C type-checking..

 */

#ifdef CONFIG_64BIT_PHYS_ADDR

#ifdef CONFIG_PHYS_ADDR_T_64BIT

  #ifdef CONFIG_CPU_MIPS32

    typedef struct { unsigned long pte_low, pte_high; } pte_t;

    #define pte_val(x)	  ((x).pte_low | ((unsigned long long)(x).pte_high << 32))

arch/mips/include/asm/pgtable-32.h

+7 −7
Original line number Diff line number Diff line
@@ -69,7 +69,7 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, 
# define VMALLOC_END	(FIXADDR_START-2*PAGE_SIZE)

#endif



#ifdef CONFIG_64BIT_PHYS_ADDR

#ifdef CONFIG_PHYS_ADDR_T_64BIT

#define pte_ERROR(e) \

	printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))

#else
@@ -103,7 +103,7 @@ static inline void pmd_clear(pmd_t *pmdp) 
	pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);

}



#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)

#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)

#define pte_page(x)		pfn_to_page(pte_pfn(x))

#define pte_pfn(x)		((unsigned long)((x).pte_high >> 6))

static inline pte_t
@@ -126,7 +126,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot) 
#define pte_pfn(x)		((unsigned long)((x).pte >> _PFN_SHIFT))

#define pfn_pte(pfn, prot)	__pte(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot))

#endif

#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */

#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */



#define __pgd_offset(address)	pgd_index(address)

#define __pud_offset(address)	(((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
@@ -177,7 +177,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot) 
#else



/* Swap entries must have VALID and GLOBAL bits cleared. */

#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)

#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)

#define __swp_type(x)		(((x).val >> 2) & 0x1f)

#define __swp_offset(x)		 ((x).val >> 7)

#define __swp_entry(type,offset)	\
@@ -187,9 +187,9 @@ pfn_pte(unsigned long pfn, pgprot_t prot) 
#define __swp_offset(x)		 ((x).val >> 13)

#define __swp_entry(type,offset)	\

		((swp_entry_t)	{ ((type) << 8) | ((offset) << 13) })

#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */

#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */



#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)

#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)

/*

 * Bits 0 and 1 of pte_high are taken, use the rest for the page offset...

 */
@@ -216,7 +216,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot) 


#endif



#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)

#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)

#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })

#define __swp_entry_to_pte(x)	((pte_t) { 0, (x).val })

#else