drm/i915/edp: use lane count and link rate from DPCD for eDP (344c5bbc) · Commits · e / devices / android_kernel_teracube_2e

eDP panels are generally designed to support only a single clock and lane configuration. commit Author: Jani Nikula <jani.nikula@intel.com> Date: Tue May 6 14:56:52 2014 +0300 drm/i915: use lane count and link rate from VBT as minimums for eDP should have started using the optimal link parameters for eDP panels. Turns out a certain other OS uses DPCD instead of VBT, which means trusting VBT on this may not be so reliable after all. Follow suit. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81647 Tested-by:

Adam Jirasek <libm3l@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79386 Tested-by:

Narthana Epa <narthana.epa+freedesktop@gmail.com> Signed-off-by:

Jani Nikula <jani.nikula@intel.com> Signed-off-by:

Daniel Vetter <daniel.vetter@ffwll.ch>

drivers/gpu/drm/i915/intel_dp.c

+9 −17

Original line number	Diff line number	Diff line
		@@ -1068,23 +1068,15 @@ intel_dp_compute_config(struct intel_encoder *encoder,
		bpp = dev_priv->vbt.edp_bpp;
		}

		if (IS_BROADWELL(dev)) {
		/* Yes, it's an ugly hack. */
		/*
		* Use the maximum clock and number of lanes the eDP panel
		* advertizes being capable of. The panels are generally
		* designed to support only a single clock and lane
		* configuration, and typically these values correspond to the
		* native resolution of the panel.
		*/
		min_lane_count = max_lane_count;
		DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
		min_lane_count);
		} else if (dev_priv->vbt.edp_lanes) {
		min_lane_count = min(dev_priv->vbt.edp_lanes,
		max_lane_count);
		DRM_DEBUG_KMS("using min %u lanes per VBT\n",
		min_lane_count);
		}

		if (dev_priv->vbt.edp_rate) {
		min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
		DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
		bws[min_clock]);
		}
		min_clock = max_clock;
		}

		for (; bpp >= 63; bpp -= 23) {