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Commit 33305373 authored by Ben Dooks's avatar Ben Dooks
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[ARM] S3C64XX: Add EINT group regs and move IRQ_EINT to regs-gpio.h 



Add definitions for the EINT group registers and move the EINT IRQ
register definitions out of arch/arm/plat-s3c64xx/irq-eint.c so that
they are available for re-use with PM and the other code.

Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
parent 5b3d515f

arch/arm/plat-s3c64xx/include/plat/regs-gpio.h

+61 −17
Original line number Diff line number Diff line
@@ -13,23 +13,67 @@ 


/* Base addresses for each of the banks */



#define S3C64XX_GPA_BASE	(S3C64XX_VA_GPIO + 0x0000)

#define S3C64XX_GPB_BASE	(S3C64XX_VA_GPIO + 0x0020)

#define S3C64XX_GPC_BASE	(S3C64XX_VA_GPIO + 0x0040)

#define S3C64XX_GPD_BASE	(S3C64XX_VA_GPIO + 0x0060)

#define S3C64XX_GPE_BASE	(S3C64XX_VA_GPIO + 0x0080)

#define S3C64XX_GPF_BASE	(S3C64XX_VA_GPIO + 0x00A0)

#define S3C64XX_GPG_BASE	(S3C64XX_VA_GPIO + 0x00C0)

#define S3C64XX_GPH_BASE	(S3C64XX_VA_GPIO + 0x00E0)

#define S3C64XX_GPI_BASE	(S3C64XX_VA_GPIO + 0x0100)

#define S3C64XX_GPJ_BASE	(S3C64XX_VA_GPIO + 0x0120)

#define S3C64XX_GPK_BASE	(S3C64XX_VA_GPIO + 0x0800)

#define S3C64XX_GPL_BASE	(S3C64XX_VA_GPIO + 0x0810)

#define S3C64XX_GPM_BASE	(S3C64XX_VA_GPIO + 0x0820)

#define S3C64XX_GPN_BASE	(S3C64XX_VA_GPIO + 0x0830)

#define S3C64XX_GPO_BASE	(S3C64XX_VA_GPIO + 0x0140)

#define S3C64XX_GPP_BASE	(S3C64XX_VA_GPIO + 0x0160)

#define S3C64XX_GPQ_BASE	(S3C64XX_VA_GPIO + 0x0180)

#define S3C64XX_GPIOREG(reg)	(S3C64XX_VA_GPIO + (reg))



#define S3C64XX_GPA_BASE	S3C64XX_GPIOREG(0x0000)

#define S3C64XX_GPB_BASE	S3C64XX_GPIOREG(0x0020)

#define S3C64XX_GPC_BASE	S3C64XX_GPIOREG(0x0040)

#define S3C64XX_GPD_BASE	S3C64XX_GPIOREG(0x0060)

#define S3C64XX_GPE_BASE	S3C64XX_GPIOREG(0x0080)

#define S3C64XX_GPF_BASE	S3C64XX_GPIOREG(0x00A0)

#define S3C64XX_GPG_BASE	S3C64XX_GPIOREG(0x00C0)

#define S3C64XX_GPH_BASE	S3C64XX_GPIOREG(0x00E0)

#define S3C64XX_GPI_BASE	S3C64XX_GPIOREG(0x0100)

#define S3C64XX_GPJ_BASE	S3C64XX_GPIOREG(0x0120)

#define S3C64XX_GPK_BASE	S3C64XX_GPIOREG(0x0800)

#define S3C64XX_GPL_BASE	S3C64XX_GPIOREG(0x0810)

#define S3C64XX_GPM_BASE	S3C64XX_GPIOREG(0x0820)

#define S3C64XX_GPN_BASE	S3C64XX_GPIOREG(0x0830)

#define S3C64XX_GPO_BASE	S3C64XX_GPIOREG(0x0140)

#define S3C64XX_GPP_BASE	S3C64XX_GPIOREG(0x0160)

#define S3C64XX_GPQ_BASE	S3C64XX_GPIOREG(0x0180)



/* External interrupt registers */



#define S3C64XX_EINT12CON	S3C64XX_GPIOREG(0x200)

#define S3C64XX_EINT34CON	S3C64XX_GPIOREG(0x204)

#define S3C64XX_EINT56CON	S3C64XX_GPIOREG(0x208)

#define S3C64XX_EINT78CON	S3C64XX_GPIOREG(0x20C)

#define S3C64XX_EINT9CON	S3C64XX_GPIOREG(0x210)



#define S3C64XX_EINT12FLTCON	S3C64XX_GPIOREG(0x220)

#define S3C64XX_EINT34FLTCON	S3C64XX_GPIOREG(0x224)

#define S3C64XX_EINT56FLTCON	S3C64XX_GPIOREG(0x228)

#define S3C64XX_EINT78FLTCON	S3C64XX_GPIOREG(0x22C)

#define S3C64XX_EINT9FLTCON	S3C64XX_GPIOREG(0x230)



#define S3C64XX_EINT12MASK	S3C64XX_GPIOREG(0x240)

#define S3C64XX_EINT34MASK	S3C64XX_GPIOREG(0x244)

#define S3C64XX_EINT56MASK	S3C64XX_GPIOREG(0x248)

#define S3C64XX_EINT78MASK	S3C64XX_GPIOREG(0x24C)

#define S3C64XX_EINT9MASK	S3C64XX_GPIOREG(0x250)



#define S3C64XX_EINT12PEND	S3C64XX_GPIOREG(0x260)

#define S3C64XX_EINT34PEND	S3C64XX_GPIOREG(0x264)

#define S3C64XX_EINT56PEND	S3C64XX_GPIOREG(0x268)

#define S3C64XX_EINT78PEND	S3C64XX_GPIOREG(0x26C)

#define S3C64XX_EINT9PEND	S3C64XX_GPIOREG(0x270)



#define S3C64XX_PRIORITY	S3C64XX_GPIOREG(0x280)

#define S3C64XX_PRIORITY_ARB(x)	(1 << (x))



#define S3C64XX_SERVICE		S3C64XX_GPIOREG(0x284)

#define S3C64XX_SERVICEPEND	S3C64XX_GPIOREG(0x288)



#define S3C64XX_EINT0CON0	S3C64XX_GPIOREG(0x900)

#define S3C64XX_EINT0CON1	S3C64XX_GPIOREG(0x904)

#define S3C64XX_EINT0FLTCON0	S3C64XX_GPIOREG(0x910)

#define S3C64XX_EINT0FLTCON1	S3C64XX_GPIOREG(0x914)

#define S3C64XX_EINT0FLTCON2	S3C64XX_GPIOREG(0x918)

#define S3C64XX_EINT0FLTCON3	S3C64XX_GPIOREG(0x91C)



#define S3C64XX_EINT0MASK	S3C64XX_GPIOREG(0x920)

#define S3C64XX_EINT0PEND	S3C64XX_GPIOREG(0x924)



#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */

arch/arm/plat-s3c64xx/irq-eint.c

+0 −14
Original line number Diff line number Diff line
@@ -27,20 +27,6 @@ 
#include <mach/map.h>

#include <plat/cpu.h>



/* GPIO is 0x7F008xxx, */

#define S3C64XX_GPIOREG(x)	(S3C64XX_VA_GPIO + (x))



#define S3C64XX_EINT0CON0	S3C64XX_GPIOREG(0x900)

#define S3C64XX_EINT0CON1	S3C64XX_GPIOREG(0x904)

#define S3C64XX_EINT0FLTCON0	S3C64XX_GPIOREG(0x910)

#define S3C64XX_EINT0FLTCON1	S3C64XX_GPIOREG(0x914)

#define S3C64XX_EINT0FLTCON2	S3C64XX_GPIOREG(0x918)

#define S3C64XX_EINT0FLTCON3	S3C64XX_GPIOREG(0x91C)



#define S3C64XX_EINT0MASK	S3C64XX_GPIOREG(0x920)

#define S3C64XX_EINT0PEND	S3C64XX_GPIOREG(0x924)





#define eint_offset(irq)	((irq) - IRQ_EINT(0))

#define eint_irq_to_bit(irq)	(1 << eint_offset(irq))