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Commit 33169312 authored by Michael Hennerich's avatar Michael Hennerich Committed by Bryan Wu
Browse files

Blackfin arch: Fix Bug - Kernel does not boot if re-program clocks 



On BF561 EBIU_SDGCTL bit 31 controls the SDRAM external data
path width, typically set 0 for a 32-bit bus width. On other
Blackfin derivatives this bit should be set by default.

Signed-off-by: default avatarMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: default avatarBryan Wu <cooloney@kernel.org>
parent 41245ac5

arch/blackfin/include/asm/mem_init.h

+1 −1
Original line number Diff line number Diff line
@@ -115,7 +115,7 @@ 
#define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)



/* Enable SCLK Out */

#define mem_SDGCTL        (0x80000000 | SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)

#define mem_SDGCTL        (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)

#else

#define mem_SDRRC 	CONFIG_MEM_SDRRC

#define mem_SDGCTL	CONFIG_MEM_SDGCTL

arch/blackfin/mach-common/clocks-init.c

+2 −1
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
#include <asm/clocks.h>

#include <asm/mem_init.h>



#define SDGCTL_WIDTH (1 << 31)	/* SDRAM external data path width */

#define PLL_CTL_VAL \

	(((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \

	 (PLL_BYPASS << 8) | (ANOMALY_05000265 ? 0x8000 : 0))
@@ -76,7 +77,7 @@ void init_clocks(void) 
	bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);

#ifdef EBIU_SDGCTL

	bfin_write_EBIU_SDRRC(mem_SDRRC);

	bfin_write_EBIU_SDGCTL(mem_SDGCTL);

	bfin_write_EBIU_SDGCTL((bfin_read_EBIU_SDGCTL() & SDGCTL_WIDTH) | mem_SDGCTL);

#else

	bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));

	do_sync();