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Commit 32eb6e8b authored by James Hogan's avatar James Hogan Committed by Ralf Baechle
Browse files

MIPS: Netlogic: Fix CP0_EBASE redefinition warnings 



A couple of netlogic assembly files define CP0_EBASE to $15, the same as
CP0_PRID in mipsregs.h, and use it for accessing both CP0_PRId and
CP0_EBase registers. However commit 609cf6f2 ("MIPS: CPS: Early
debug using an ns16550-compatible UART") added a different definition of
CP0_EBASE to mipsregs.h, which included a register select of 1. This
causes harmless build warnings like the following:

  arch/mips/netlogic/common/reset.S:53:0: warning: "CP0_EBASE" redefined
  #define CP0_EBASE $15
  ^
  In file included from arch/mips/netlogic/common/reset.S:41:0:
  ./arch/mips/include/asm/mipsregs.h:63:0: note: this is the location of the previous definition
  #define CP0_EBASE $15, 1
  ^

Update the code to use the definitions from mipsregs.h for accessing
both registers.

Fixes: 609cf6f2 ("MIPS: CPS: Early debug using an ns16550-compatible UART")
Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
Acked-by: default avatarJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13183/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 12863939

arch/mips/netlogic/common/reset.S

+5 −6
Original line number Diff line number Diff line
@@ -50,7 +50,6 @@ 
#include <asm/netlogic/xlp-hal/sys.h>

#include <asm/netlogic/xlp-hal/cpucontrol.h>



#define CP0_EBASE	$15

#define SYS_CPU_COHERENT_BASE	CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \

			XLP_IO_SYS_OFFSET(0) + XLP_IO_PCI_HDRSZ + \

			SYS_CPU_NONCOHERENT_MODE * 4
@@ -92,7 +91,7 @@ 
 * registers. On XLPII CPUs, usual cache instructions work.

 */

.macro	xlp_flush_l1_dcache

	mfc0	t0, CP0_EBASE, 0

	mfc0	t0, CP0_PRID

	andi	t0, t0, PRID_IMP_MASK

	slt	t1, t0, 0x1200

	beqz	t1, 15f
@@ -171,7 +170,7 @@ FEXPORT(nlm_reset_entry) 
	nop



1:	/* Entry point on core wakeup */

	mfc0	t0, CP0_EBASE, 0	/* processor ID */

	mfc0	t0, CP0_PRID		/* processor ID */

	andi	t0, PRID_IMP_MASK

	li	t1, 0x1500		/* XLP 9xx */

	beq	t0, t1, 2f		/* does not need to set coherent */
@@ -182,8 +181,8 @@ FEXPORT(nlm_reset_entry) 
	nop



	/* set bit in SYS coherent register for the core */

	mfc0	t0, CP0_EBASE, 1

	mfc0	t1, CP0_EBASE, 1

	mfc0	t0, CP0_EBASE

	mfc0	t1, CP0_EBASE

	srl	t1, 5

	andi	t1, 0x3			/* t1 <- node */

	li	t2, 0x40000
@@ -232,7 +231,7 @@ EXPORT(nlm_boot_siblings) 


	 * NOTE: All GPR contents are lost after the mtcr above!

	 */

	mfc0	v0, CP0_EBASE, 1

	mfc0	v0, CP0_EBASE

	andi	v0, 0x3ff		/* v0 <- node/core */



	/*

arch/mips/netlogic/common/smpboot.S

+1 −3
Original line number Diff line number Diff line
@@ -48,8 +48,6 @@ 
#include <asm/netlogic/xlp-hal/sys.h>

#include <asm/netlogic/xlp-hal/cpucontrol.h>



#define CP0_EBASE	$15



	.set	noreorder

	.set	noat

	.set	arch=xlr		/* for mfcr/mtcr, XLR is sufficient */
@@ -86,7 +84,7 @@ NESTED(nlm_boot_secondary_cpus, 16, sp) 
	PTR_L	gp, 0(t1)



	/* a0 has the processor id */

	mfc0	a0, CP0_EBASE, 1

	mfc0	a0, CP0_EBASE

	andi	a0, 0x3ff		/* a0 <- node/core */

	PTR_LA	t0, nlm_early_init_secondary

	jalr	t0