Commit 32cf0cb0 authored Nov 28, 2013 by Ville Syrjälä Committed by Daniel Vetter Nov 28, 2013

drm/i915: Fix pipe CSC post offset calculation

We were miscalculating the pipe CSC post offset for the full->limited
range conversion. The resulting post offset was double what it was
supposed to be, which caused blacks to come out grey when using
limited range output on HSW+.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71769


Cc: stable@vger.kernel.org
Tested-by: Lauri Mylläri <lauri.myllari@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

parent 3b32a35b

drivers/gpu/drm/i915/intel_display.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -5815,7 +5815,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc)
		uint16_t postoff = 0;

		if (intel_crtc->config.limited_color_range)
		postoff = (16 * (1 << 13) / 255) & 0x1fff;
		postoff = (16 * (1 << 12) / 255) & 0x1fff;

		I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);