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Commit 323cbb09 authored by Russ Anderson's avatar Russ Anderson Committed by Tony Luck
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[IA64] Add dp bit to cache and bus check structs 



Rev 2.2 of Volume 2 of "Intel Itanium Architecture Software Developer's
Manual" (January 2006) adds a dp bit to the cache_check and bus_check
fields (pages 2:401-2:404).  This patch gets the structs back in sync
with the spec.

Signed-off-by: default avatarRuss Anderson <(rja@sgi.com)>
Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
parent c6957771

include/asm-ia64/pal.h

+5 −3
Original line number Diff line number Diff line
@@ -487,10 +487,12 @@ typedef struct pal_cache_check_info_s { 
						 * error occurred

						 */

			wiv		: 1,	/* Way field valid */

			reserved2	: 10,

			reserved2	: 1,

			dp		: 1,	/* Data poisoned on MBE */

			reserved3	: 8,



			index		: 20,	/* Cache line index */

			reserved3	: 2,

			reserved4	: 2,



			is		: 1,	/* instruction set (1 == ia32) */

			iv		: 1,	/* instruction set field valid */
@@ -557,7 +559,7 @@ typedef struct pal_bus_check_info_s { 
			type		: 8,	/* Bus xaction type*/

			sev		: 5,	/* Bus error severity*/

			hier		: 2,	/* Bus hierarchy level */

			reserved1	: 1,

			dp		: 1,	/* Data poisoned on MBE */

			bsi		: 8,	/* Bus error status

						 * info

						 */