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Commit 3148ade7 authored by Damien Lespiau's avatar Damien Lespiau Committed by Daniel Vetter
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drm/i915/skl: Read out crtl1 for eDP/DPLL0 



v2: Put the DPLL0 state readout in skylake_get_ddi_pll(), closer to
where the PLL assignement read out is done rather than the frequency
readout function. (Daniel)

v3: Remove stray new line (Damien)
    Add Paulo's r-b tag for v1

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 00f0b378

drivers/gpu/drm/i915/intel_display.c

+10 −1
Original line number Diff line number Diff line
@@ -8058,12 +8058,21 @@ static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, 
				enum port port,

				struct intel_crtc_config *pipe_config)

{

	u32 temp;

	u32 temp, dpll_ctl1;



	temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);

	pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);



	switch (pipe_config->ddi_pll_sel) {

	case SKL_DPLL0:

		/*

		 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part

		 * of the shared DPLL framework and thus needs to be read out

		 * separately

		 */

		dpll_ctl1 = I915_READ(DPLL_CTRL1);

		pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;

		break;

	case SKL_DPLL1:

		pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;

		break;