Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 307a2e9a authored by Jeffy Chen's avatar Jeffy Chen Committed by Heiko Stuebner
Browse files

clk: rockchip: add clock controller for rk3228 



Add the clock tree definition for the new rk3228 SoC.

Signed-off-by: default avatarJeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 80afed27

drivers/clk/rockchip/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -12,5 +12,6 @@ obj-$(CONFIG_RESET_CONTROLLER) += softrst.o 


obj-y	+= clk-rk3036.o

obj-y	+= clk-rk3188.o

obj-y	+= clk-rk3228.o

obj-y	+= clk-rk3288.o

obj-y	+= clk-rk3368.o

drivers/clk/rockchip/clk-rk3228.c

0 → 100644
+678 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/clk/rockchip/clk.h

+10 −1
Original line number Diff line number Diff line
@@ -33,7 +33,7 @@ struct clk; 
#define HIWORD_UPDATE(val, mask, shift) \

		((val) << (shift) | (mask) << ((shift) + 16))



/* register positions shared by RK2928, RK3036, RK3066 and RK3188 */

/* register positions shared by RK2928, RK3036, RK3066, RK3188 and RK3228 */

#define RK2928_PLL_CON(x)		((x) * 0x4)

#define RK2928_MODE_CON		0x40

#define RK2928_CLKSEL_CON(x)	((x) * 0x4 + 0x44)
@@ -50,6 +50,15 @@ struct clk; 
#define RK3036_EMMC_CON0		0x154

#define RK3036_EMMC_CON1		0x158



#define RK3228_GLB_SRST_FST		0x1f0

#define RK3228_GLB_SRST_SND		0x1f4

#define RK3228_SDMMC_CON0		0x1c0

#define RK3228_SDMMC_CON1		0x1c4

#define RK3228_SDIO_CON0		0x1c8

#define RK3228_SDIO_CON1		0x1cc

#define RK3228_EMMC_CON0		0x1d8

#define RK3228_EMMC_CON1		0x1dc



#define RK3288_PLL_CON(x)		RK2928_PLL_CON(x)

#define RK3288_MODE_CON			0x50

#define RK3288_CLKSEL_CON(x)		((x) * 0x4 + 0x60)