Commit 30037f66 authored Oct 30, 2005 by Venkatesh Pallipadi Committed by Linus Torvalds Oct 30, 2005

[PATCH] x86: when L3 is present show its size in /proc/cpuinfo



The code that prints the cache size assumes that L3 always lives in chipset
and is shared across CPUs.  Which is not really true.

I think all the cachesizes reported by cpuid are in the processor itself.
The attached patch changes the code to reflect that.

Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

parent f014a556

arch/i386/kernel/cpu/intel_cacheinfo.c

+1 −7

Original line number	Diff line number	Diff line
		@@ -278,13 +278,7 @@ unsigned int __devinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
		if ( l3 )
		printk(KERN_INFO "CPU: L3 cache: %dK\n", l3);

		/*
		* This assumes the L3 cache is shared; it typically lives in
		* the northbridge. The L1 caches are included by the L2
		* cache, and so should not be included for the purpose of
		* SMP switching weights.
		*/
		c->x86_cache_size = l2 ? l2 : (l1i+l1d);
		c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d));
		}

		return l2;