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Commit 2f9992e0 authored by Boris Brezillon's avatar Boris Brezillon
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mtd: nand: sunxi: fix clk rate calculation 



Unlike what is specified in the Allwinner datasheets, the NAND clock rate
is not equal to 2/T but 1/T. Fix the clock rate selection accordingly.

Signed-off-by: default avatarBoris Brezillon <boris.brezillon@free-electrons.com>
parent 9edb4700

drivers/mtd/nand/sunxi_nand.c

+5 −5
Original line number Original line Diff line number Diff line
@@ -1208,12 +1208,12 @@ static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip, 
	min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);

	min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);





	/*

	/*

	 * Convert min_clk_period into a clk frequency, then get the

	 * Unlike what is stated in Allwinner datasheet, the clk_rate should

	 * appropriate rate for the NAND controller IP given this formula

	 * be set to (1 / min_clk_period), and not (2 / min_clk_period).

	 * (specified in the datasheet):

	 * This new formula was verified with a scope and validated by

	 * nand clk_rate = 2 * min_clk_rate

	 * Allwinner engineers.

	 */

	 */

	chip->clk_rate = (2 * NSEC_PER_SEC) / min_clk_period;

	chip->clk_rate = NSEC_PER_SEC / min_clk_period;





	return 0;

	return 0;

}

}