Loading drivers/net/wireless/ti/wl1251/sdio.c +3 −1 Original line number Diff line number Diff line Loading @@ -186,8 +186,10 @@ static int wl1251_sdio_set_power(struct wl1251 *wl, bool enable) wl->set_power(true); ret = pm_runtime_get_sync(&func->dev); if (ret < 0) if (ret < 0) { pm_runtime_put_sync(&func->dev); goto out; } sdio_claim_host(func); sdio_enable_func(func); Loading drivers/net/wireless/ti/wl12xx/main.c +1 −0 Original line number Diff line number Diff line Loading @@ -723,6 +723,7 @@ static int wl12xx_identify_chip(struct wl1271 *wl) wl->sched_scan_templ_id_2_4 = CMD_TEMPL_CFG_PROBE_REQ_2_4; wl->sched_scan_templ_id_5 = CMD_TEMPL_CFG_PROBE_REQ_5; wl->max_channels_5 = WL12XX_MAX_CHANNELS_5GHZ; wl->ba_rx_session_count_max = WL12XX_RX_BA_MAX_SESSIONS; out: return ret; } Loading drivers/net/wireless/ti/wl12xx/wl12xx.h +2 −0 Original line number Diff line number Diff line Loading @@ -63,6 +63,8 @@ #define WL12XX_NUM_MAC_ADDRESSES 2 #define WL12XX_RX_BA_MAX_SESSIONS 3 struct wl127x_rx_mem_pool_addr { u32 addr; u32 addr_extra; Loading drivers/net/wireless/ti/wl18xx/main.c +24 −1 Original line number Diff line number Diff line Loading @@ -678,6 +678,7 @@ static int wl18xx_identify_chip(struct wl1271 *wl) wl->sched_scan_templ_id_2_4 = CMD_TEMPL_PROBE_REQ_2_4_PERIODIC; wl->sched_scan_templ_id_5 = CMD_TEMPL_PROBE_REQ_5_PERIODIC; wl->max_channels_5 = WL18XX_MAX_CHANNELS_5GHZ; wl->ba_rx_session_count_max = WL18XX_RX_BA_MAX_SESSIONS; out: return ret; } Loading Loading @@ -1144,6 +1145,7 @@ static u32 wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 *wl, static int wl18xx_get_pg_ver(struct wl1271 *wl, s8 *ver) { u32 fuse; s8 rom = 0, metal = 0, pg_ver = 0, rdl_ver = 0; int ret; ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]); Loading @@ -1154,8 +1156,29 @@ static int wl18xx_get_pg_ver(struct wl1271 *wl, s8 *ver) if (ret < 0) goto out; pg_ver = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET; rom = (fuse & WL18XX_ROM_VER_MASK) >> WL18XX_ROM_VER_OFFSET; if (rom <= 0xE) metal = (fuse & WL18XX_METAL_VER_MASK) >> WL18XX_METAL_VER_OFFSET; else metal = (fuse & WL18XX_NEW_METAL_VER_MASK) >> WL18XX_NEW_METAL_VER_OFFSET; ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_2_3, &fuse); if (ret < 0) goto out; rdl_ver = (fuse & WL18XX_RDL_VER_MASK) >> WL18XX_RDL_VER_OFFSET; if (rdl_ver > RDL_MAX) rdl_ver = RDL_NONE; wl1271_info("wl18xx HW: RDL %d, %s, PG %x.%x (ROM %x)", rdl_ver, rdl_names[rdl_ver], pg_ver, metal, rom); if (ver) *ver = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET; *ver = pg_ver; ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]); Loading drivers/net/wireless/ti/wl18xx/reg.h +29 −0 Original line number Diff line number Diff line Loading @@ -131,6 +131,16 @@ #define WL18XX_REG_FUSE_DATA_1_3 0xA0260C #define WL18XX_PG_VER_MASK 0x70 #define WL18XX_PG_VER_OFFSET 4 #define WL18XX_ROM_VER_MASK 0x3 #define WL18XX_ROM_VER_OFFSET 0 #define WL18XX_METAL_VER_MASK 0xC #define WL18XX_METAL_VER_OFFSET 2 #define WL18XX_NEW_METAL_VER_MASK 0x180 #define WL18XX_NEW_METAL_VER_OFFSET 7 #define WL18XX_REG_FUSE_DATA_2_3 0xA02614 #define WL18XX_RDL_VER_MASK 0x1f00 #define WL18XX_RDL_VER_OFFSET 8 #define WL18XX_REG_FUSE_BD_ADDR_1 0xA02602 #define WL18XX_REG_FUSE_BD_ADDR_2 0xA02606 Loading Loading @@ -188,4 +198,23 @@ enum { NUM_BOARD_TYPES, }; enum { RDL_NONE = 0, RDL_1_HP = 1, RDL_2_SP = 2, RDL_3_HP = 3, RDL_4_SP = 4, _RDL_LAST, RDL_MAX = _RDL_LAST - 1, }; static const char * const rdl_names[] = { [RDL_NONE] = "", [RDL_1_HP] = "1853 SISO", [RDL_2_SP] = "1857 MIMO", [RDL_3_HP] = "1893 SISO", [RDL_4_SP] = "1897 MIMO", }; #endif /* __REG_H__ */ Loading
drivers/net/wireless/ti/wl1251/sdio.c +3 −1 Original line number Diff line number Diff line Loading @@ -186,8 +186,10 @@ static int wl1251_sdio_set_power(struct wl1251 *wl, bool enable) wl->set_power(true); ret = pm_runtime_get_sync(&func->dev); if (ret < 0) if (ret < 0) { pm_runtime_put_sync(&func->dev); goto out; } sdio_claim_host(func); sdio_enable_func(func); Loading
drivers/net/wireless/ti/wl12xx/main.c +1 −0 Original line number Diff line number Diff line Loading @@ -723,6 +723,7 @@ static int wl12xx_identify_chip(struct wl1271 *wl) wl->sched_scan_templ_id_2_4 = CMD_TEMPL_CFG_PROBE_REQ_2_4; wl->sched_scan_templ_id_5 = CMD_TEMPL_CFG_PROBE_REQ_5; wl->max_channels_5 = WL12XX_MAX_CHANNELS_5GHZ; wl->ba_rx_session_count_max = WL12XX_RX_BA_MAX_SESSIONS; out: return ret; } Loading
drivers/net/wireless/ti/wl12xx/wl12xx.h +2 −0 Original line number Diff line number Diff line Loading @@ -63,6 +63,8 @@ #define WL12XX_NUM_MAC_ADDRESSES 2 #define WL12XX_RX_BA_MAX_SESSIONS 3 struct wl127x_rx_mem_pool_addr { u32 addr; u32 addr_extra; Loading
drivers/net/wireless/ti/wl18xx/main.c +24 −1 Original line number Diff line number Diff line Loading @@ -678,6 +678,7 @@ static int wl18xx_identify_chip(struct wl1271 *wl) wl->sched_scan_templ_id_2_4 = CMD_TEMPL_PROBE_REQ_2_4_PERIODIC; wl->sched_scan_templ_id_5 = CMD_TEMPL_PROBE_REQ_5_PERIODIC; wl->max_channels_5 = WL18XX_MAX_CHANNELS_5GHZ; wl->ba_rx_session_count_max = WL18XX_RX_BA_MAX_SESSIONS; out: return ret; } Loading Loading @@ -1144,6 +1145,7 @@ static u32 wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 *wl, static int wl18xx_get_pg_ver(struct wl1271 *wl, s8 *ver) { u32 fuse; s8 rom = 0, metal = 0, pg_ver = 0, rdl_ver = 0; int ret; ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]); Loading @@ -1154,8 +1156,29 @@ static int wl18xx_get_pg_ver(struct wl1271 *wl, s8 *ver) if (ret < 0) goto out; pg_ver = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET; rom = (fuse & WL18XX_ROM_VER_MASK) >> WL18XX_ROM_VER_OFFSET; if (rom <= 0xE) metal = (fuse & WL18XX_METAL_VER_MASK) >> WL18XX_METAL_VER_OFFSET; else metal = (fuse & WL18XX_NEW_METAL_VER_MASK) >> WL18XX_NEW_METAL_VER_OFFSET; ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_2_3, &fuse); if (ret < 0) goto out; rdl_ver = (fuse & WL18XX_RDL_VER_MASK) >> WL18XX_RDL_VER_OFFSET; if (rdl_ver > RDL_MAX) rdl_ver = RDL_NONE; wl1271_info("wl18xx HW: RDL %d, %s, PG %x.%x (ROM %x)", rdl_ver, rdl_names[rdl_ver], pg_ver, metal, rom); if (ver) *ver = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET; *ver = pg_ver; ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]); Loading
drivers/net/wireless/ti/wl18xx/reg.h +29 −0 Original line number Diff line number Diff line Loading @@ -131,6 +131,16 @@ #define WL18XX_REG_FUSE_DATA_1_3 0xA0260C #define WL18XX_PG_VER_MASK 0x70 #define WL18XX_PG_VER_OFFSET 4 #define WL18XX_ROM_VER_MASK 0x3 #define WL18XX_ROM_VER_OFFSET 0 #define WL18XX_METAL_VER_MASK 0xC #define WL18XX_METAL_VER_OFFSET 2 #define WL18XX_NEW_METAL_VER_MASK 0x180 #define WL18XX_NEW_METAL_VER_OFFSET 7 #define WL18XX_REG_FUSE_DATA_2_3 0xA02614 #define WL18XX_RDL_VER_MASK 0x1f00 #define WL18XX_RDL_VER_OFFSET 8 #define WL18XX_REG_FUSE_BD_ADDR_1 0xA02602 #define WL18XX_REG_FUSE_BD_ADDR_2 0xA02606 Loading Loading @@ -188,4 +198,23 @@ enum { NUM_BOARD_TYPES, }; enum { RDL_NONE = 0, RDL_1_HP = 1, RDL_2_SP = 2, RDL_3_HP = 3, RDL_4_SP = 4, _RDL_LAST, RDL_MAX = _RDL_LAST - 1, }; static const char * const rdl_names[] = { [RDL_NONE] = "", [RDL_1_HP] = "1853 SISO", [RDL_2_SP] = "1857 MIMO", [RDL_3_HP] = "1893 SISO", [RDL_4_SP] = "1897 MIMO", }; #endif /* __REG_H__ */