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Commit 2e8ecdc0 authored by David S. Miller's avatar David S. Miller
Browse files

sparc64: Fix masking and shifting in VIS fpcmp emulation. 



Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent a52312b8

arch/sparc/kernel/visemul.c

+16 −16
Original line number Diff line number Diff line
@@ -713,17 +713,17 @@ static void pcmp(struct pt_regs *regs, unsigned int insn, unsigned int opf) 
			s16 b = (rs2 >> (i * 16)) & 0xffff;



			if (a > b)

				rd_val |= 1 << i;

				rd_val |= 8 >> i;

		}

		break;



	case FCMPGT32_OPF:

		for (i = 0; i < 2; i++) {

			s32 a = (rs1 >> (i * 32)) & 0xffff;

			s32 b = (rs2 >> (i * 32)) & 0xffff;

			s32 a = (rs1 >> (i * 32)) & 0xffffffff;

			s32 b = (rs2 >> (i * 32)) & 0xffffffff;



			if (a > b)

				rd_val |= 1 << i;

				rd_val |= 2 >> i;

		}

		break;
@@ -733,17 +733,17 @@ static void pcmp(struct pt_regs *regs, unsigned int insn, unsigned int opf) 
			s16 b = (rs2 >> (i * 16)) & 0xffff;



			if (a <= b)

				rd_val |= 1 << i;

				rd_val |= 8 >> i;

		}

		break;



	case FCMPLE32_OPF:

		for (i = 0; i < 2; i++) {

			s32 a = (rs1 >> (i * 32)) & 0xffff;

			s32 b = (rs2 >> (i * 32)) & 0xffff;

			s32 a = (rs1 >> (i * 32)) & 0xffffffff;

			s32 b = (rs2 >> (i * 32)) & 0xffffffff;



			if (a <= b)

				rd_val |= 1 << i;

				rd_val |= 2 >> i;

		}

		break;
@@ -753,17 +753,17 @@ static void pcmp(struct pt_regs *regs, unsigned int insn, unsigned int opf) 
			s16 b = (rs2 >> (i * 16)) & 0xffff;



			if (a != b)

				rd_val |= 1 << i;

				rd_val |= 8 >> i;

		}

		break;



	case FCMPNE32_OPF:

		for (i = 0; i < 2; i++) {

			s32 a = (rs1 >> (i * 32)) & 0xffff;

			s32 b = (rs2 >> (i * 32)) & 0xffff;

			s32 a = (rs1 >> (i * 32)) & 0xffffffff;

			s32 b = (rs2 >> (i * 32)) & 0xffffffff;



			if (a != b)

				rd_val |= 1 << i;

				rd_val |= 2 >> i;

		}

		break;
@@ -773,17 +773,17 @@ static void pcmp(struct pt_regs *regs, unsigned int insn, unsigned int opf) 
			s16 b = (rs2 >> (i * 16)) & 0xffff;



			if (a == b)

				rd_val |= 1 << i;

				rd_val |= 8 >> i;

		}

		break;



	case FCMPEQ32_OPF:

		for (i = 0; i < 2; i++) {

			s32 a = (rs1 >> (i * 32)) & 0xffff;

			s32 b = (rs2 >> (i * 32)) & 0xffff;

			s32 a = (rs1 >> (i * 32)) & 0xffffffff;

			s32 b = (rs2 >> (i * 32)) & 0xffffffff;



			if (a == b)

				rd_val |= 1 << i;

				rd_val |= 2 >> i;

		}

		break;

	}