Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 2e568f56 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'tegra-for-3.20-arm64' of... 

Merge tag 'tegra-for-3.20-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/arm64

Merge "arm64: Add initial Tegra support" from Thierry Reding:

This adds support for the Tegra132 SoC, which is essentially a Tegra124
with a dual Denver CPU complex instead of the quad-Cortex-A15. There is
not much here, only the Kconfig entries, but it will allow us to more
easily get subsequent patches in (many of which have already been sent
for review).

* tag 'tegra-for-3.20-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux

:
  arm64: Add Tegra132 support
  soc: tegra: Add thermal reset (thermtrip) support to PMC
  ARM: tegra: Add PMC thermtrip programming to Jetson TK1 device tree
  of: Add descriptions of thermtrip properties to Tegra PMC bindings
  soc/tegra: pmc: Add Tegra132 support
  soc/tegra: fuse: Add Tegra132 support
  soc/tegra: fuse: Constify tegra_fuse_info structures
  soc/tegra: Add Tegra132 support
  clocksource: Build Tegra timer on 32-bit ARM only
  soc/tegra: pmc: restrict compilation of suspend-related support to ARM

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents ff3a45b6 d035fdfa

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt

+26 −0
Original line number Diff line number Diff line
@@ -47,6 +47,23 @@ Required properties when nvidia,suspend-mode=<0>: 
  sleep mode, the warm boot code will restore some PLLs, clocks and then

  bring up CPU0 for resuming the system.



Hardware-triggered thermal reset:

On Tegra30, Tegra114 and Tegra124, if the 'i2c-thermtrip' subnode exists,

hardware-triggered thermal reset will be enabled.



Required properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):

- nvidia,i2c-controller-id : ID of I2C controller to send poweroff command to. Valid values are

                             described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0" of the

                             Tegra K1 Technical Reference Manual.

- nvidia,bus-addr : Bus address of the PMU on the I2C bus

- nvidia,reg-addr : I2C register address to write poweroff command to

- nvidia,reg-data : Poweroff command to write to PMU



Optional properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):

- nvidia,pinmux-id : Pinmux used by the hardware when issuing poweroff command.

                     Defaults to 0. Valid values are described in section 12.5.2

                     "Pinmux Support" of the Tegra4 Technical Reference Manual.



Example:



/ SoC dts including file
@@ -68,6 +85,15 @@ pmc@7000f400 { 


/ Tegra board dts file

{

	...

	pmc@7000f400 {

		i2c-thermtrip {

			nvidia,i2c-controller-id = <4>;

			nvidia,bus-addr = <0x40>;

			nvidia,reg-addr = <0x36>;

			nvidia,reg-data = <0x2>;

		};

	};

	...

	clocks {

		compatible = "simple-bus";

arch/arm/boot/dts/tegra124-jetson-tk1.dts

+7 −0
Original line number Diff line number Diff line
@@ -1673,6 +1673,13 @@ 
		nvidia,core-pwr-off-time = <61036>;

		nvidia,core-power-req-active-high;

		nvidia,sys-clock-req-active-high;



		i2c-thermtrip {

			nvidia,i2c-controller-id = <4>;

			nvidia,bus-addr = <0x40>;

			nvidia,reg-addr = <0x36>;

			nvidia,reg-data = <0x2>;

		};

	};



	/* Serial ATA */

arch/arm/mach-tegra/Kconfig

+4 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ config ARCH_TEGRA_2x_SOC 
	select PINCTRL_TEGRA20

	select PL310_ERRATA_727915 if CACHE_L2X0

	select PL310_ERRATA_769419 if CACHE_L2X0

	select TEGRA_TIMER

	help

	  Support for NVIDIA Tegra AP20 and T20 processors, based on the

	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
@@ -37,6 +38,7 @@ config ARCH_TEGRA_3x_SOC 
	select ARM_ERRATA_764369 if SMP

	select PINCTRL_TEGRA30

	select PL310_ERRATA_769419 if CACHE_L2X0

	select TEGRA_TIMER

	help

	  Support for NVIDIA Tegra T30 processor family, based on the

	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
@@ -47,6 +49,7 @@ config ARCH_TEGRA_114_SOC 
	select ARM_L1_CACHE_SHIFT_6

	select HAVE_ARM_ARCH_TIMER

	select PINCTRL_TEGRA114

	select TEGRA_TIMER

	help

	  Support for NVIDIA Tegra T114 processor family, based on the

	  ARM CortexA15MP CPU
@@ -56,6 +59,7 @@ config ARCH_TEGRA_124_SOC 
	select ARM_L1_CACHE_SHIFT_6

	select HAVE_ARM_ARCH_TIMER

	select PINCTRL_TEGRA124

	select TEGRA_TIMER

	help

	  Support for NVIDIA Tegra T124 processor family, based on the

	  ARM CortexA15MP CPU

arch/arm64/Kconfig

+28 −0
Original line number Diff line number Diff line
@@ -170,6 +170,34 @@ config ARCH_SEATTLE 
	help

	  This enables support for AMD Seattle SOC Family



config ARCH_TEGRA

	bool "NVIDIA Tegra SoC Family"

	select ARCH_HAS_RESET_CONTROLLER

	select ARCH_REQUIRE_GPIOLIB

	select CLKDEV_LOOKUP

	select CLKSRC_MMIO

	select CLKSRC_OF

	select GENERIC_CLOCKEVENTS

	select HAVE_CLK

	select HAVE_SMP

	select PINCTRL

	select RESET_CONTROLLER

	help

	  This enables support for the NVIDIA Tegra SoC family.



config ARCH_TEGRA_132_SOC

	bool "NVIDIA Tegra132 SoC"

	depends on ARCH_TEGRA

	select PINCTRL_TEGRA124

	select USB_ARCH_HAS_EHCI if USB_SUPPORT

	select USB_ULPI if USB_PHY

	select USB_ULPI_VIEWPORT if USB_PHY

	help

	  Enable support for NVIDIA Tegra132 SoC, based on the Denver

	  ARMv8 CPU.  The Tegra132 SoC is similar to the Tegra124 SoC,

	  but contains an NVIDIA Denver CPU complex in place of

	  Tegra124's "4+1" Cortex-A15 CPU complex.



config ARCH_THUNDER

	bool "Cavium Inc. Thunder SoC Family"

	help

drivers/clocksource/Kconfig

+3 −0
Original line number Diff line number Diff line
@@ -47,6 +47,9 @@ config SUN5I_HSTIMER 
	select CLKSRC_MMIO

	bool



config TEGRA_TIMER

	bool



config VT8500_TIMER

	bool