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Commit 2d8a9c9c authored by Thierry Reding's avatar Thierry Reding
Browse files

ARM: tegra: Add Tegra124 XUSB controller 



Add a device tree node for the Tegra XUSB controller. It contains a
phandle to the XUSB pad controller for control of the PHYs assigned
to the USB ports.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 50623c59

arch/arm/boot/dts/tegra124.dtsi

+35 −0
Original line number Diff line number Diff line
@@ -636,6 +636,41 @@ 
		status = "disabled";

	};



	usb@0,70090000 {

		compatible = "nvidia,tegra124-xusb";

		reg = <0x0 0x70090000 0x0 0x8000>,

		      <0x0 0x70098000 0x0 0x1000>,

		      <0x0 0x70099000 0x0 0x1000>;

		reg-names = "hcd", "fpci", "ipfs";



		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;



		clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,

			 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,

			 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,

			 <&tegra_car TEGRA124_CLK_XUSB_SS>,

			 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,

			 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,

			 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,

			 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,

			 <&tegra_car TEGRA124_CLK_PLL_U_480M>,

			 <&tegra_car TEGRA124_CLK_CLK_M>,

			 <&tegra_car TEGRA124_CLK_PLL_E>;

		clock-names = "xusb_host", "xusb_host_src",

			      "xusb_falcon_src", "xusb_ss",

			      "xusb_ss_div2", "xusb_ss_src",

			      "xusb_hs_src", "xusb_fs_src",

			      "pll_u_480m", "clk_m", "pll_e";

		resets = <&tegra_car 89>, <&tegra_car 156>,

			 <&tegra_car 143>;

		reset-names = "xusb_host", "xusb_ss", "xusb_src";



		nvidia,xusb-padctl = <&padctl>;



		status = "disabled";

	};



	padctl: padctl@0,7009f000 {

		compatible = "nvidia,tegra124-xusb-padctl";

		reg = <0x0 0x7009f000 0x0 0x1000>;