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Commit 2d370f50 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge remote branch 'intel/drm-intel-fixes' of ../drm-next into drm-core-next 

* 'intel/drm-intel-fixes' of ../drm-next:
  Revert "drm/i915: Don't save/restore hardware status page address register"
  drm/i915: Avoid unmapping pages from a NULL address space
  drm/i915: Fix use after free within tracepoint
  drm/i915: Restore missing command flush before interrupt on BLT ring
  drm/i915: Disable pagefaults along execbuffer relocation fast path
  drm/i915: Fix computation of pitch for dumb bo creator
  drm/i915: report correct render clock frequencies on SNB
  drm/i915/dp: Correct the order of deletion for ghost eDP devices
  drm/i915: Fix tiling corruption from pipelined fencing
  drm/i915: Re-enable self-refresh
  drm/i915: Prevent racy removal of request from client list
  drm/i915: skip redundant operations whilst enabling pipes and planes
  drm/i915: Remove surplus POSTING_READs before wait_for_vblank
parents 64146f8b f0c86024

drivers/gpu/drm/i915/i915_debugfs.c

+4 −4
Original line number Diff line number Diff line
@@ -892,7 +892,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) 
		seq_printf(m, "Render p-state limit: %d\n",

			   rp_state_limits & 0xff);

		seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>

						GEN6_CAGF_SHIFT) * 100);

						GEN6_CAGF_SHIFT) * 50);

		seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &

			   GEN6_CURICONT_MASK);

		seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
@@ -908,15 +908,15 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) 


		max_freq = (rp_state_cap & 0xff0000) >> 16;

		seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",

			   max_freq * 100);

			   max_freq * 50);



		max_freq = (rp_state_cap & 0xff00) >> 8;

		seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",

			   max_freq * 100);

			   max_freq * 50);



		max_freq = rp_state_cap & 0xff;

		seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",

			   max_freq * 100);

			   max_freq * 50);



		__gen6_gt_force_wake_put(dev_priv);

	} else {

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -383,6 +383,7 @@ typedef struct drm_i915_private { 
	u32 saveDSPACNTR;

	u32 saveDSPBCNTR;

	u32 saveDSPARB;

	u32 saveHWS;

	u32 savePIPEACONF;

	u32 savePIPEBCONF;

	u32 savePIPEASRC;

drivers/gpu/drm/i915/i915_gem.c

+34 −36
Original line number Diff line number Diff line
@@ -224,7 +224,7 @@ i915_gem_dumb_create(struct drm_file *file, 
		     struct drm_mode_create_dumb *args)

{

	/* have to work out size/pitch and return them */

	args->pitch = ALIGN(args->width & ((args->bpp + 1) / 8), 64);

	args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);

	args->size = args->pitch * args->height;

	return i915_gem_create(file, dev,

			       args->size, &args->handle);
@@ -1356,6 +1356,7 @@ i915_gem_release_mmap(struct drm_i915_gem_object *obj) 
	if (!obj->fault_mappable)

		return;



	if (obj->base.dev->dev_mapping)

		unmap_mapping_range(obj->base.dev->dev_mapping,

				    (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,

				    obj->base.size, 1);
@@ -1796,8 +1797,10 @@ i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) 
		return;



	spin_lock(&file_priv->mm.lock);

	if (request->file_priv) {

		list_del(&request->client_list);

		request->file_priv = NULL;

	}

	spin_unlock(&file_priv->mm.lock);

}
@@ -2217,13 +2220,18 @@ i915_gem_flush_ring(struct intel_ring_buffer *ring, 
{

	int ret;



	if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)

		return 0;



	trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains);



	ret = ring->flush(ring, invalidate_domains, flush_domains);

	if (ret)

		return ret;



	if (flush_domains & I915_GEM_GPU_DOMAINS)

		i915_gem_process_flushing_list(ring, flush_domains);



	return 0;

}
@@ -2579,9 +2587,24 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj, 
		reg = &dev_priv->fence_regs[obj->fence_reg];

		list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);



		if (obj->tiling_changed) {

			ret = i915_gem_object_flush_fence(obj, pipelined);

			if (ret)

				return ret;



			if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)

				pipelined = NULL;



			if (pipelined) {

				reg->setup_seqno =

					i915_gem_next_request_seqno(pipelined);

				obj->last_fenced_seqno = reg->setup_seqno;

				obj->last_fenced_ring = pipelined;

			}



			goto update;

		}



		if (!pipelined) {

			if (reg->setup_seqno) {

				if (!ring_passed_seqno(obj->last_fenced_ring,
@@ -2599,31 +2622,6 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj, 
			ret = i915_gem_object_flush_fence(obj, pipelined);

			if (ret)

				return ret;

		} else if (obj->tiling_changed) {

			if (obj->fenced_gpu_access) {

				if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {

					ret = i915_gem_flush_ring(obj->ring,

								  0, obj->base.write_domain);

					if (ret)

						return ret;

				}



				obj->fenced_gpu_access = false;

			}

		}



		if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)

			pipelined = NULL;

		BUG_ON(!pipelined && reg->setup_seqno);



		if (obj->tiling_changed) {

			if (pipelined) {

				reg->setup_seqno =

					i915_gem_next_request_seqno(pipelined);

				obj->last_fenced_seqno = reg->setup_seqno;

				obj->last_fenced_ring = pipelined;

			}

			goto update;

		}



		return 0;
@@ -3606,6 +3604,8 @@ static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj) 
		return;

	}



	trace_i915_gem_object_destroy(obj);



	if (obj->base.map_list.map)

		i915_gem_free_mmap_offset(obj);
@@ -3615,8 +3615,6 @@ static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj) 
	kfree(obj->page_cpu_valid);

	kfree(obj->bit_17);

	kfree(obj);



	trace_i915_gem_object_destroy(obj);

}



void i915_gem_free_object(struct drm_gem_object *gem_obj)

drivers/gpu/drm/i915/i915_gem_execbuffer.c

+17 −4
Original line number Diff line number Diff line
@@ -367,6 +367,10 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, 
		uint32_t __iomem *reloc_entry;

		void __iomem *reloc_page;



		/* We can't wait for rendering with pagefaults disabled */

		if (obj->active && in_atomic())

			return -EFAULT;



		ret = i915_gem_object_set_to_gtt_domain(obj, 1);

		if (ret)

			return ret;
@@ -440,15 +444,24 @@ i915_gem_execbuffer_relocate(struct drm_device *dev, 
			     struct list_head *objects)

{

	struct drm_i915_gem_object *obj;

	int ret;



	int ret = 0;



	/* This is the fast path and we cannot handle a pagefault whilst

	 * holding the struct mutex lest the user pass in the relocations

	 * contained within a mmaped bo. For in such a case we, the page

	 * fault handler would call i915_gem_fault() and we would try to

	 * acquire the struct mutex again. Obviously this is bad and so

	 * lockdep complains vehemently.

	 */

	pagefault_disable();

	list_for_each_entry(obj, objects, exec_list) {

		ret = i915_gem_execbuffer_relocate_object(obj, eb);

		if (ret)

			return ret;

			break;

	}

	pagefault_enable();



	return 0;

	return ret;

}



static int

drivers/gpu/drm/i915/i915_suspend.c

+6 −0
Original line number Diff line number Diff line
@@ -796,6 +796,9 @@ int i915_save_state(struct drm_device *dev) 


	pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);



	/* Hardware status page */

	dev_priv->saveHWS = I915_READ(HWS_PGA);



	i915_save_display(dev);



	/* Interrupt state */
@@ -842,6 +845,9 @@ int i915_restore_state(struct drm_device *dev) 


	pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);



	/* Hardware status page */

	I915_WRITE(HWS_PGA, dev_priv->saveHWS);



	i915_restore_display(dev);



	/* Interrupt state */