Merge tag 'for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next

Device tree binding documentation for am816x USB PHY

=========================

Required properties:

- compatible : should be "ti,dm816x-usb-phy"

- reg : offset and length of the PHY register set.

- reg-names : name for the phy registers

- clocks : phandle to the clock

- clock-names : name of the clock

- syscon: phandle for the syscon node to access misc registers

- #phy-cells : from the generic PHY bindings, must be 1

- syscon: phandle for the syscon node to access misc registers

Example:

usb_phy0: usb-phy@20 {

	compatible = "ti,dm8168-usb-phy";

	reg = <0x20 0x8>;

	reg-names = "phy";

	clocks = <&main_fapll 6>;

	clock-names = "refclk";

	#phy-cells = <0>;

	syscon = <&scm_conf>;

};

Required properties (port (child) node):

- #phy-cells 	: Should be 1 (See second example)

		  Cell after port phandle is device type from:

			- MIPHY_TYPE_SATA

			- MIPHY_TYPE_PCI

			- PHY_TYPE_SATA

			- PHY_TYPE_PCI

- reg        	: Address and length of register sets for each device in

		  "reg-names"

- reg-names     : The names of the register addresses corresponding to the

Example:

#include <dt-bindings/phy/phy-miphy365x.h>

#include <dt-bindings/phy/phy.h>

	sata0: sata@fe380000 {

		...

		phys	  = <&phy_port0 MIPHY_TYPE_SATA>;

		phys	  = <&phy_port0 PHY_TYPE_SATA>;

		...

	};

- compatible : Should be set to one of the following supported values:

	- "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC,

	- "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC.

	- "samsung,exynos5433-usbdrd-phy" - for exynos5433 SoC.

	- "samsung,exynos7-usbdrd-phy" - for exynos7 SoC.

- reg : Register offset and length of USB DRD PHY register set;

- clocks: Clock IDs array as required by the controller

	       PHY operations, associated by phy name. It is used to

	       determine bit values for clock settings register.

	       For Exynos5420 this is given as 'sclk_usbphy30' in CMU.

	- optional clocks: Exynos7 SoC has now following additional

	- optional clocks: Exynos5433 & Exynos7 SoC has now following additional

			   gate clocks available:

			   - phy_pipe: for PIPE3 phy

			   - phy_utmi: for UTMI+ phy

Allwinner sun9i USB PHY

-----------------------

Required properties:

- compatible : should be one of

  * allwinner,sun9i-a80-usb-phy

- reg : a list of offset + length pairs

- #phy-cells : from the generic phy bindings, must be 0

- phy_type : "hsic" for HSIC usage;

	     other values or absence of this property indicates normal USB

- clocks : phandle + clock specifier for the phy clocks

- clock-names : depending on the "phy_type" property,

  * "phy" for normal USB

  * "hsic_480M", "hsic_12M" for HSIC

- resets : a list of phandle + reset specifier pairs

- reset-names : depending on the "phy_type" property,

  * "phy" for normal USB

  * "hsic" for HSIC

Optional Properties:

- phy-supply : from the generic phy bindings, a phandle to a regulator that

	       provides power to VBUS.

It is recommended to list all clocks and resets available.

The driver will only use those matching the phy_type.

Example:

	usbphy1: phy@00a01800 {

		compatible = "allwinner,sun9i-a80-usb-phy";

		reg = <0x00a01800 0x4>;

		clocks = <&usb_phy_clk 2>, <&usb_phy_clk 10>,

		       <&usb_phy_clk 3>;

		clock-names = "hsic_480M", "hsic_12M", "phy";

		resets = <&usb_phy_clk 18>, <&usb_phy_clk 19>;

		reset-names = "hsic", "phy";

		status = "disabled";

		#phy-cells = <0>;

	};

F:	drivers/i2c/busses/i2c-st.c

F:	drivers/media/rc/st_rc.c

F:	drivers/mmc/host/sdhci-st.c

F:	drivers/phy/phy-miphy28lp.c

F:	drivers/phy/phy-miphy365x.c

F:	drivers/phy/phy-stih407-usb.c

F:	drivers/phy/phy-stih41x-usb.c

F:	drivers/pinctrl/pinctrl-st.c