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Commit 2a21dc7c authored by Huacai Chen's avatar Huacai Chen Committed by Ralf Baechle
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MIPS: Hibernate: flush TLB entries earlier 



We found that TLB mismatch not only happens after kernel resume, but
also happens during snapshot restore. So move it to the beginning of
swsusp_arch_suspend().

Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
Cc: <stable@vger.kernel.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9621/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 4c9164b9

arch/mips/power/hibernate.S

+2 −1
Original line number Original line Diff line number Diff line
@@ -30,6 +30,8 @@ LEAF(swsusp_arch_suspend) 
END(swsusp_arch_suspend)

END(swsusp_arch_suspend)





LEAF(swsusp_arch_resume)

LEAF(swsusp_arch_resume)

	/* Avoid TLB mismatch during and after kernel resume */

	jal local_flush_tlb_all

	PTR_L t0, restore_pblist

	PTR_L t0, restore_pblist

0:

0:

	PTR_L t1, PBE_ADDRESS(t0)   /* source */

	PTR_L t1, PBE_ADDRESS(t0)   /* source */
@@ -43,7 +45,6 @@ LEAF(swsusp_arch_resume) 
	bne t1, t3, 1b

	bne t1, t3, 1b

	PTR_L t0, PBE_NEXT(t0)

	PTR_L t0, PBE_NEXT(t0)

	bnez t0, 0b

	bnez t0, 0b

	jal local_flush_tlb_all /* Avoid TLB mismatch after kernel resume */

	PTR_LA t0, saved_regs

	PTR_LA t0, saved_regs

	PTR_L ra, PT_R31(t0)

	PTR_L ra, PT_R31(t0)

	PTR_L sp, PT_R29(t0)

	PTR_L sp, PT_R29(t0)