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Commit 29848ac9 authored by Martyn Welch's avatar Martyn Welch Committed by Greg Kroah-Hartman
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Staging: vme: Enable drivers to handle more than one bridge



At the moment the vme bridge drivers are written in a way that only
allows them to support one bridge at a time. Modify the drivers to
enable more than one bridge to be present per board.

Signed-off-by: default avatarMartyn Welch <martyn.welch@ge.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 4f723df4
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+0 −2
Original line number Diff line number Diff line
@@ -47,7 +47,6 @@ Bridge Support
Tempe (tsi148)
--------------

- Driver can currently only support a single bridge.
- 2eSST Broadcast mode.
- Mailboxes unsupported.
- Improve error detection.
@@ -58,7 +57,6 @@ Tempe (tsi148)
Universe II (ca91c142)
----------------------

- Driver can currently only support a single bridge.
- DMA unsupported.
- RMW transactions unsupported.
- Location Monitors unsupported.
+232 −179

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Original line number Diff line number Diff line
@@ -37,6 +37,22 @@
#define CA91C142_MAX_DMA		1	/* Max DMA Controllers */
#define CA91C142_MAX_MAILBOX		4	/* Max Mail Box registers */

/* Structure used to hold driver specific information */
struct ca91cx42_driver {
	void *base;	/* Base Address of device registers */
	wait_queue_head_t dma_queue;
	wait_queue_head_t iack_queue;
	wait_queue_head_t mbox_queue;
	void (*lm_callback[4])(int);	/* Called in interrupt handler */
	void *crcsr_kernel;
	dma_addr_t crcsr_bus;
	struct mutex vme_rmw;		/* Only one RMW cycle at a time */
	struct mutex vme_int;		/*
					 * Only one VME interrupt can be
					 * generated at a time, provide locking
					 */
};

/* See Page 2-77 in the Universe User Manual */
struct ca91cx42_dma_descriptor {
	unsigned int dctl;      /* DMA Control */
+360 −274

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@@ -33,6 +33,22 @@
#define TSI148_MAX_MAILBOX		4	/* Max Mail Box registers */
#define TSI148_MAX_SEMAPHORE		8	/* Max Semaphores */

/* Structure used to hold driver specific information */
struct tsi148_driver {
	void *base;	/* Base Address of device registers */
	wait_queue_head_t dma_queue[2];
	wait_queue_head_t iack_queue;
	void (*lm_callback[4])(int);	/* Called in interrupt handler */
	void *crcsr_kernel;
	dma_addr_t crcsr_bus;
	struct vme_master_resource *flush_image;
	struct mutex vme_rmw;		/* Only one RMW cycle at a time */
	struct mutex vme_int;		/*
					 * Only one VME interrupt can be
					 * generated at a time, provide locking
					 */
};

/*
 * Layout of a DMAC Linked-List Descriptor
 *
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