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Commit 29569941 authored by Jon Hunter's avatar Jon Hunter Committed by Thierry Reding
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clk: tegra: Add the APB2APE audio clock on Tegra210



The APB2APE clock for the audio subsystem is required for powering up the
audio power domain and accessing the various modules in this subsystem on
Tegra210 devices. Add this clock for Tegra210.

Signed-off-by: default avatarJon Hunter <jonathanh@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 047d6d84
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+1 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ enum clk_id {
	tegra_clk_afi,
	tegra_clk_amx,
	tegra_clk_amx1,
	tegra_clk_apb2ape,
	tegra_clk_apbdma,
	tegra_clk_apbif,
	tegra_clk_ape,
+1 −0
Original line number Diff line number Diff line
@@ -829,6 +829,7 @@ static struct tegra_periph_init_data gate_clks[] = {
	GATE("xusb_gate", "osc", 143, 0, tegra_clk_xusb_gate, 0),
	GATE("pll_p_out_cpu", "pll_p", 223, 0, tegra_clk_pll_p_out_cpu, 0),
	GATE("pll_p_out_adsp", "pll_p", 187, 0, tegra_clk_pll_p_out_adsp, 0),
	GATE("apb2ape", "clk_m", 107, 0, tegra_clk_apb2ape, 0),
};

static struct tegra_periph_init_data div_clks[] = {
+1 −0
Original line number Diff line number Diff line
@@ -2204,6 +2204,7 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
	[tegra_clk_pll_c4_out1] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT1, .present = true },
	[tegra_clk_pll_c4_out2] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT2, .present = true },
	[tegra_clk_pll_c4_out3] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT3, .present = true },
	[tegra_clk_apb2ape] = { .dt_id = TEGRA210_CLK_APB2APE, .present = true },
};

static struct tegra_devclk devclks[] __initdata = {
+1 −1
Original line number Diff line number Diff line
@@ -126,7 +126,7 @@
/* 104 */
/* 105 */
#define TEGRA210_CLK_D_AUDIO 106
/* 107 ( affects abp -> ape) */
#define TEGRA210_CLK_APB2APE 107
/* 108 */
/* 109 */
/* 110 */