Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 291427f5 authored by Jesse Barnes's avatar Jesse Barnes Committed by Keith Packard
Browse files

drm/i915: apply phase pointer override on SNB+ too 



These bits moved around on SNB and above.

v2: again with the git send-email fail
v3: add macros for getting per-pipe override & enable bits
v4: enable phase sync pointer on SNB and IVB configs as well

Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarKeith Packard <keithp@keithp.com>
parent 070d329a

drivers/gpu/drm/i915/i915_reg.h

+5 −0
Original line number Diff line number Diff line
@@ -3091,6 +3091,11 @@ 
#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)

#define   TRANS_AUTOTRAIN_GEN_STALL_DIS	(1<<31)



#define SOUTH_CHICKEN1		0xc2000

#define  FDIA_PHASE_SYNC_SHIFT_OVR	19

#define  FDIA_PHASE_SYNC_SHIFT_EN	18

#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))

#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))

#define SOUTH_CHICKEN2		0xc2004

#define  DPLS_EDP_PPS_FIX_DIS	(1<<0)

drivers/gpu/drm/i915/intel_display.c

+31 −0
Original line number Diff line number Diff line
@@ -2113,6 +2113,18 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc) 
			   FDI_FE_ERRC_ENABLE);

}



static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 flags = I915_READ(SOUTH_CHICKEN1);



	flags |= FDI_PHASE_SYNC_OVR(pipe);

	I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */

	flags |= FDI_PHASE_SYNC_EN(pipe);

	I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */

	POSTING_READ(SOUTH_CHICKEN1);

}



/* The FDI link training functions for ILK/Ibexpeak. */

static void ironlake_fdi_link_train(struct drm_crtc *crtc)

{
@@ -2263,6 +2275,9 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc) 
	POSTING_READ(reg);

	udelay(150);



	if (HAS_PCH_CPT(dev))

		cpt_phase_pointer_enable(dev, pipe);



	for (i = 0; i < 4; i++ ) {

		reg = FDI_TX_CTL(pipe);

		temp = I915_READ(reg);
@@ -2379,6 +2394,9 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) 
	POSTING_READ(reg);

	udelay(150);



	if (HAS_PCH_CPT(dev))

		cpt_phase_pointer_enable(dev, pipe);



	for (i = 0; i < 4; i++ ) {

		reg = FDI_TX_CTL(pipe);

		temp = I915_READ(reg);
@@ -2488,6 +2506,17 @@ static void ironlake_fdi_pll_enable(struct drm_crtc *crtc) 
	}

}



static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 flags = I915_READ(SOUTH_CHICKEN1);



	flags &= ~(FDI_PHASE_SYNC_EN(pipe));

	I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */

	flags &= ~(FDI_PHASE_SYNC_OVR(pipe));

	I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */

	POSTING_READ(SOUTH_CHICKEN1);

}

static void ironlake_fdi_disable(struct drm_crtc *crtc)

{

	struct drm_device *dev = crtc->dev;
@@ -2517,6 +2546,8 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc) 
		I915_WRITE(FDI_RX_CHICKEN(pipe),

			   I915_READ(FDI_RX_CHICKEN(pipe) &

				     ~FDI_RX_PHASE_SYNC_POINTER_EN));

	} else if (HAS_PCH_CPT(dev)) {

		cpt_phase_pointer_disable(dev, pipe);

	}



	/* still set train pattern 1 */