Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 28cf5415 authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
Browse files

drm/i915/bdw: unleash PPGTT 



v2: Squash in fix from Ben: Set PPGTT batches as necessary

This fixes the regression in the last couple of days when we enabled
PPGTT.

v3: Squash in fixup to still use GTT for secure batches from Ville:

BDW doesn't have a separate secure vs. non-secure bit in
MI_BATCH_BUFFER_START. So for secure batches we have to simply
leave the PPGTT bit unset. Fortunately older generations (except
HSW) had similar limitations so execbuffer already creates a GTT
mapping for all secure batches.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 94e409c1

drivers/gpu/drm/i915/i915_gem_execbuffer.c

+1 −2
Original line number Diff line number Diff line
@@ -1146,8 +1146,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, 


	/* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure

	 * batch" bit. Hence we need to pin secure batches into the global gtt.

	 * hsw should have this fixed, but let's be paranoid and do it

	 * unconditionally for now. */

	 * hsw should have this fixed, but bdw mucks it up again. */

	if (flags & I915_DISPATCH_SECURE && !batch_obj->has_global_gtt_mapping)

		i915_gem_gtt_bind_object(batch_obj, batch_obj->cache_level);

drivers/gpu/drm/i915/i915_gem_gtt.c

+1 −1
Original line number Diff line number Diff line
@@ -439,7 +439,7 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) 
			 ppgtt->num_pt_pages,

			 (ppgtt->num_pt_pages - num_pt_pages) +

			 size % (1<<30));

	return -ENOSYS; /* Not ready yet */

	return 0;



err_out:

	ppgtt->base.cleanup(&ppgtt->base);

drivers/gpu/drm/i915/intel_ringbuffer.c

+4 −1
Original line number Diff line number Diff line
@@ -1699,6 +1699,9 @@ gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, 
			      u32 offset, u32 len,

			      unsigned flags)

{

	struct drm_i915_private *dev_priv = ring->dev->dev_private;

	bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL &&

		!(flags & I915_DISPATCH_SECURE);

	int ret;



	ret = intel_ring_begin(ring, 4);
@@ -1706,7 +1709,7 @@ gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, 
		return ret;



	/* FIXME(BDW): Address space and security selectors. */

	intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8);

	intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));

	intel_ring_emit(ring, offset);

	intel_ring_emit(ring, 0);

	intel_ring_emit(ring, MI_NOOP);